Research And Implementation Of Parallel Simulation Acceleration System Based On Gate-Level Netlist

Electronic design automation(EDA)is a basic tool software system widely used in the entire integrated circuit industry chain.It is listed as the three strategic pillars of the integrated circuit industry along with equipment and materials,and directly affects the performance,quality,and production efficiency and cost.As the core part of the whole process of EDA software,gate-level simulation verification directly determines the length of the large-scale integrated circuit chip design cycle.Aiming at the problems of insufficient gate-level netlist syntax analysis and too long simulation verification cycle in traditional gate-level simulation verification,this paper proposes a gate-level parallel simulation acceleration method for digital circuits based on semantic directed graph,and it is used in multi-core processors(Central processing unit(CPU)experiment platform achieved several times parallel acceleration.This paper also further explores the main factors affecting the parallel acceleration effect of gate-level simulation through multiple sets of experiments,providing theoretical and experimental data support for the deep mining of the parallel acceleration potential.The main research work of this paper is as follows:First,the acceleration theory and related work of gate-level parallel simulation are reviewed,and the deficiencies of existing gate-level simulation in terms of gate-level netlist syntax analysis and parallel simulation scheme selection are clarified.In terms of gate-level netlist syntax analysis,this paper expounds the three-step theoretical method of lexical analysis,syntax analysis,and storage of analysis results,analyzes the existing classic work in each step,and points out its shortcomings.In terms of the selection of parallel simulation schemes,this paper uses hardware architecture as a distinction,respectively expounds the implementation of different gate-level parallel simulation schemes based on CPU and graphics processing unit(GPU)hardware architectures,and summarizes the limitations of different schemes.The common difficulties of parallel acceleration lay the theoretical foundation for the semantic translation and parallel simulator design in the following sections.Secondly,two parts,gate-level netlist semantic translator and semantic directed graph parallel simulator,are designed to realize gate-level netlist parallel simulation acceleration.The design idea of semantic translator is to propose the concept of semantic translation by studying the mapping relationship between gate-level netlist hardware description language and gate-level simulation.That is,the circuit information in the gate-level netlist is analyzed at the semantic level based on gatelevel simulation,and it is translated into a directed graph containing gate-level semantic information,which solves the workload of gate-level netlist analysis at the existing grammar level problems such as large size,insufficient completeness of results,and excessive redundancy.At the same time,this paper also performs a general structural representation process on the results after semantic translation,avoiding the defect that the gate-level netlist analysis results cannot be generalized due to the inconsistency in form.The design of the parallel simulator follows the inherent parallel logic of the gatelevel netlist,and a new event-driven parallel simulation algorithm is proposed to ensure the scalability of the parallel simulation acceleration scheme.Finally,this paper builds an experimental circuit data set based on standard circuit sets and common gate-level IP modules.Through testing on the multi-core CPU experimental platform,several times the parallel acceleration of the million-level gate scale has been achieved,and the system is scalable for future larger-scale gate-level netlist simulation verification,and by changing the circuit size,parallel threads The number and other dependent variables are discussed,and the main factors affecting the parallel acceleration effect are discussed,and the optimal strategy solution for gatelevel parallel simulation under different conditions is further searched.