Research On Gate-level Netlist Based Hardwear Trojan Detection Technology

With the development of integrated circuits and globalizaton of integrated circuit design and product, it have raised serious concerns about vulnerabilities of integrated circuit. It has been affected some national security that due to vulnerabilities of integrated circuit, so it’s very necessary to carry out the research on detection techniques of hardware Trojans.Hardware Trojans can be inserted in ICs at the RTL during design specification, at the gate level during DFT insertion, at the layout level during placement and routing or during IC manufacturing. It can be implented as hadware modifications to application specific integrated circuits(ASICs), commercial off-the-shelf(COTS) parts or microprocessors. Due to the gate- level netlist of integrated circuits can be acquired, so we carried out the research on detection techniques of Trojans on the gate-level netlist. The main works are as follows:1.According to the classification of the trigger circuit and executive circuit of trojans, complete analyzing and abstracting the feat ure of hardware Trojans. Then through analyzing the different functional modules of circuit under detect(C UD), and determine the scope of trojans detection technology application which on t he basis of gate-level netlist.2.It is accroding to analysis of the circuit function and hardware Trojans structure that we complete detecting the suspicious signal include abnormal ports, asynchronous circuit, undetectable block, low transition probabilities of signals and so on.3.According to the equivalence principle of ATPG,complete removing the equivalent signal and redundant signal,reducing the number of suspicious signal. Then the suspicious signals are divided into module according to correlation of them. Considering the scale and feature of module, we can use the method of topology or simulation to acquire transition probability of it. And through transition probability to evaluate the suspiciou module. It is be expected to reduce the number of suspicious signals. In the last, the method of amendment of suspiciou signals is proposed, so that acquire hardware Trojans as much intergrity as possible.4.Through the semantic analysis of the gate-level netlist, which is stored in memory in the form of adjacency list, and complete separating clock network,reset network and logic network. Through analyzing circuit and abstract feature of gate- level netlist so that its data structure is determined.5.Completing hierarchical suspicious module and host circuit. Then analyze the connection relation between the m. We realized analysis and validation hardware Trojans according simulation of suspicious module and gate-level netlist feature6.The techniques implemented in Trojans detecting on the gate- level netlist are encapsulated by a graphical user interface(GUI) available to the user. The GUI was developed to be simple and straightforward while still providing the features needed to execute detecting on the gate-level netlist.