Subgraph Isomorphic To The Transistor-level Circuit Gate-level Model Extraction

With the development of VLSI, the complexity of circuits makes automatally abstraction of a gate model from its transistor netlist more and more important. In traditional application, the gate model is used for functional simulation, which is much less time consuming than transistor level simulation; and in formal verification, especially in equivalence checking, the gate model plays a very important role. Therefore, a good way of abstraction should be researched. As we known, the method based on subgragh isomorphism is a promising way at present. It maps a circuit into a graph, which can reduce the time complexity and improve the abstraction ability.In this thesis, the abstraction of a gate model from its transistor netlist is discussed systematically. Meanwhile, we make improvement and implementation on DECIDE algorithm and get some conclusions and achievements. The main content of the thesis is as follows:1. Two kinds of main methods of abstraction are studied, analyzed and compared. And we carry on carefully the theoretical research and systematic analysis of the method based on subgraph isomorphism. In addition, we carry on improvement and implementation of DECIDE algorithm.2. According to the project's requirement, we analyze the technological difficult points while realizing it, and propose a new realization scheme. Meanwhile, we carry on feasibility analysis and provide systematic block diagram.3. According to the system specification, the function modules of the system are analyzed and implemented, including input block, matching block and output block. Besides, the access and storage method of operands is redesigned in terms of data characteristic.4. We carry on performance analysis of the abstraction, including the timing complexity and memory, then system testing is carried on and the experimental results are analyzed.5. The general work of this thesis is summarized and directions for future investigation are outlined.