Design And Implementation Of A Partitioning-Based 3D Placer

As integrated circuit technology continues to develop,the interconnection issue has become a bottleneck of affecting chip performance.The 3D IC technology provides designers with a new design approach that can effectively reduce the wirelength,reduce timing delays and improve chip performance,which currently recognized as the new development direction of the integrated circuits.In the three-dimensional chip design process,placement is important parts of the physical design,but designers lack EDA tools to effectively support for three-dimensional chip design.Therefore,it is so important to research the placement technology of the three-dimensional chip,which can improve the performance of the chip.Compared with the traditional two-dimensional chips,three-dimensional chip has a special three-dimensional structure,so three-dimensional chip design can not simply copy the two-dimensional chip design technology.Moreover the placement issues need to research and develop new three-dimensional placement algorithm.This thesis chooses three-dimensional chip placement technology as the research direction,combined with domestic and foreign circumstance of placement technology.First,this thesis researches the two-dimensional benchmark of ISPD,and designs the three-dimensional conversion method based on the folding,which converts the two-dimensional benchmark into 3D benchmark as the basis of the research of three-dimensional placer.Then,it designs a three-dimensional placer based on partitioning,complete three-dimensional placement of the chip and evaluate the interconnect length of placement.The results showed that: firstly compared with the "Kraftwerk" two-dimensional placer,the three-dimensional placer based on partitioning reduces HPWL by 35.02%.Second,compared with the three-dimensional placer based on folding,the three-dimensional placer based on partitioning reduces HPWL by 26.60% and runtime by 26.81%.The three-dimensional placer based on partitioning will provide theoretical and technical support for our own national research and development of three-dimensional chip.