Physical Design Factors That Contribute to Routing Congestion in Monolithic 3D Integrated Circuits

Over the last five decades, there has been major technological progress in semiconductor industry. According to Moore's law, the number of transistors on an Integrated Circuit (IC) doubles every two years. Integrated circuits technologies constantly continue to shrink in order to improve performance and meet the need for increased functionality. However, the difficulty of integration threatens to derail the trend of improving circuit performance in future generations Therefore, by using Three-Dimensional Integrated Circuit (3D-IC), the functionality and performance of new technologies can continue the trajectory predicted by the Moore's law. Three-dimensional integration provides a promising solution to maintain higher integration by bonding multiple silicon chips vertically to form an integrated stack. Three-dimensional integration enables more transistors to be placed in a reduced silicon area than two-dimension designs. This thesis focuses on one type of 3D-ICs, monolithic 3D. Monolithic 3D integrated circuits process all the functions in a single semiconductor manufacturing flow, which allows for finer integration, at the transistor level, than existing 3D-ICs.;Despite monolithic 3D-IC offering many performance benefits over existing technologies, it currently faces some design challenges that inhibit it from exploiting these benefits. One of the major problems in the monolithic 3D-IC is wire routing congestion, which hinders the performance, yield, and cost of a circuit. Designing a three-dimensional circuit enables a reduction in cell area, wire and distance between logic gates. The increase in routing is due to increased cell density and reduced chip area, which degrades the routability. The goal of this research is to improve the feasibility of monolithic 3D-ICs by further investigating different characteristics that impact the physical design of monolithic 3D-ICs. In this thesis, the accuracy of early-stage estimation metrics for large-scale 3D-ICs is investigated. It is vital in large designs to predict congestion before routing is performed. This research also investigated technology-mapping and physical designs factors that impact routing congestion. Relevant design factors are identified and manipulated throughout the design flow to alleviate congestion. Final results indicate that modifying the physical layout and design algorithms can reduce routing congestion.