Physical Unclonable Hardware (PUF)Security Technology For FPGAs

With the rapid development of electronic information technology,physical entities of various electronic devices,such as smart cards,frequency identification tags,and sensor network nodes,have become more and more widely used.The emergence of hardware security issues is particularly important,and brings even greater challenges to the IT industry with high requirements for hardware security,such as automotive electronics and avionics.At present,traditional encryption algorithms such as AES,RSA,and digital signature are generally based on the key.The key is usually stored in non-volatile memory,but this storage method is very vulnerable to non-intrusive attacks.In view of this background,the concept of PUF(Physical Unclonable Function)authentication was proposed by using the unique human characteristics such as fingerprint and iris to authenticate individuals.PUF has a wide range of application prospects in the field of hardware security due to its own unclonable,tamper-resistant,lightweight,and many other good attributes.Firstly,this thesis makes deep research and analysis on the basic concepts,performance parameters,classical structure and basic application of Physical Unclonable Functions.The PUF performance parameters include uniqueness,uniformity,reliability,and bit aliasing.PUF classical structure is divided into non-electronics,analog circuits and digital circuits.Common basic PUF applications include Intellectual Property(IP)protection,random number generators,device authentication,and key generation.Secondly,this thesis studies the concepts of the path switch and the non-path switch,and analyzes the traditional arbiter PUF.Based on the analysis of the traditional arbiter PUF,the overall scheme of the FPGA implementation of the arbiter PUF based on PDL(programmable delay line)is given.Due to the defects of FPGA's automatic layout and routing,the two paths of the arbiter's PUF circuit cannot be completely symmetrical,and an arbiter PUF with an adaptive circuit module is designed.The PDL-based arbiter PUF consists of a PDL module,an excitation generation module,and an adaptive circuit module.The design of the PDL module includes the realization of the hardware description language of the PDL and the production flow of the PDL Hard Macro.At the same time,two methods of implementing the linear feedback shift register are introduced in the design of the excitation generation module.Finally,based on the ISE 14.7 kit as a development and simulation tool,the module functional simulation results are given.And based on the PDL arbiter PUF experimental results on the FPGA are analyzed.The simulation and verification results show that after the adaptive circuit is added,the uniformity and uniqueness of PUF based on PDL arbiter have been significantly improved.Uniformity reached 48.95%and uniqueness reached 49.23%.