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Energy-Efficient Management For Memory System Based On Access Patterns Of Applications

Posted on:2014-07-30Degree:DoctorType:Dissertation
Country:ChinaCandidate:T F ZhangFull Text:PDF
GTID:1268330425486525Subject:Computer Science and Technology
Abstract/Summary:PDF Full Text Request
The development of computer architecture is driven by the progress of semi-conductor technology and the computing power requirement of the applications. The memory system plays a key role in the computer architecture since it provides instructions and data to the processors. To keep in pace with the speed of the processor, the memory hierarchy, both the on-chip cache and the off-chip memory, become more complex and larger. Thus the memory hierarchy consumes a large portion of the system energy. Since the energy issue becomes a major constraint in current computer system design, the energy consumption of memory system demands a great amount of attention.Most current researches focus on the on-chip cache and the main memory since these two are the most energy-hungry. The manufactory provides memory banking and low-power state for the main memory to save energy. Besides, the non-volatile memory has advantages such as low leakage power and high density. To combine the strengths of non-volatile memory and DRAM, the hybrid PCM/DRAM memory has been proposed. And the non-volatile memory, STT-RAM, has been adopted for energy-efficient cache memory design.In this dissertation, we studied the memory access patterns of applications, including how the application accesses the physical pages in the main memory, how the processor writes the cache block and how the application writes the physical pages. Based on those access patterns and the existing works, we make the following contributions:1.Firstly, we propose an OS-based methodology to reduce the energy overhead caused by memory mode transitions. In particular, we propose an algorithm to optimize the executing order of processes to reduce the number of memory mode transitions as well as to create long idle intervals for energy saving. Secondly, we extend the work to the multi-core devices. In particular, the processes are scheduled based on their memory access characteristics to maximize the number of the memory banks being in low power mode. A fast approximation algorithm and two heuristic algorithms are proposed.2. Firstly, we studied the pattern of the write accesses from CPU to cache and then propose a Selective Read-Before-Write (SRW) scheme to further reduce the dynamic write energy of the STT-RAM cache. Additional optimizations are included in the design of SRW so that it can save a considerable amount of energy at negligible overheads. To address the write energy of multi-lelve STT-RAM, we propose Companion Write Cache(CWC), which is a small fully associative SRAM cache, to absorb the energy-consuming write updates from the MLC STT-RAM cache.3. Firstly, we studied the write access pattern within each physical page and found two typical write patterns. Then we propose an adaptive data migration strategy for hybrid PCM/DRAM main memory. The basic idea is to detect the write pattern of the physical page and then migrate the write-hot data of the page using different granularities instead of whole-page granularity alone. Secondly, we propose a partial data refresh management to reduce the energy consumption of DRAM. Based on the data migration information, the refresh controller of the DRAM is modified so that it is aware of the valid data within its refresh unit and then only performs data refresh operation over those valid data to save energy.At last, we evaluated the proposed strategies and technique with practical platform such as PandaBoard, full system simulator like Gem5, SESC, CACTI and so on. Experimental results show that the proposed techniques and organizations help to save more energy of the memory system compared to the existing schemes.In this dissertation, we study and observe the access patterns of applications, including how the applications access the memory banks, how the applications write the cache block and how the applications write the physical page. Based on these found patterns, we propose novel techniques and organizations to exploit the energy-saving potential of the existing hardware. The experimental results demonstrate that our proposals can help to save more energy compared to the existing techniques.
Keywords/Search Tags:energy-efficient, cache, main memory, non-volatile memory, memoryaccess pattern, scheduler, hybrid main memory
PDF Full Text Request
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