CMOS RF Power Amplifier Research And Design Approaches For LTE Applications

For many years III–V semiconductors were essential to realize monolithic microwave integrated circuits(MMICs),mainly of the CaAs type.However,the wireless market is highly competitive resulting in a dramatic change of emphasis with silicon becoming the material of choice for microwave wireless transceivers because of the importance of low cost and analogue-digital integration,as well as its continuously improving high-frequency performance.Today techniques,such as guard-rings and deep-trench isolation around individual building blocks,have ameliorated the problems with standard bulk CMOS that the substrate is not insulating;passive components have very poor performance,and coupling through the substrate.Remarkably,processing innovations have allowed an increase intrinsic gain in recent technologies.Furthermore,silicon technology is able to satisfy the noise figure requirements for sensitive applications,and in many cases the power and efficiency requirements as well.Its advantages,however,come at the cost of continuously reduced breakdown voltages,low isolation and high power loss in the substrate.This dissertation focuses on the design of high-linearity CMOS power amplifiers(PAs)for LTE wireless handsets using IBM 180 nm SOI(Silicon On Insulator)CMOS process,where stringent linearity requirements and high power efficiency are difficult to achieve simultaneously.To address the limitations of CMOS,a two-stages stacked-FET structure is first presented.In order to improve the linearity and efficiency of SOI PAs,elaborately designed a pseudo class-F matching network by emerging high order harmonic traps.Then a pseudo parallel-connected stacked-FET structure for large-power application is demonstrated.The proposed pseudo structure can effectively eliminate the problems of thermal diffusion leaded by the intrinsic drawback of CMOS.The proposed two-stage Class-F power amplifier is implemented with driver and power stage.The driver stage is a triple-stacked FETs while power stage is a quadruple structure.The stacked technique can divide the voltage stress among several transistors connected in series,allowing the use of a larger supply voltage.The voltage swing of each stacked device is added in phase to provide a larger output power to the load without the requirement of a large impedance transformation.The optimum load impedance for a 30 d Bm power amplifier is about 10.6 ? that the output matching network can be realized easily.Simulation of a twostage linear power amplifier shows a small-signal gain of 28.8 dB and a saturated output power of 30 dBm with a power added efficiency(PAE)of 48.0% at 2.35 GHz.