| In today's rapidly changing world with emerging technologies, there is an increasing demand in computer performance. Many applications in the areas of graph theory, digital control, signal processing, and image processing require enormous computing power. It can be observed that most of the applications involve matrix computations.; Matrix multiplication is one of the essential and fundamental arithmetic operations in a wide range of applications. Many complex scientific computation applications require floating point representation of values and floating point arithmetic. It is very inefficient if the arithmetic processing is done using software on the core central processing unit. The hardware implementation of such a processor makes computations efficient and versatile. Consequently techniques that provide efficient computing on the hardware are required. The advancement in the processor speed and size allows for the implementation of fixed-point as well as floating point computations simultaneously. This thesis aims at developing hardware architecture for floating point as well as fixed-point matrix multiplication, which is reconfigurable with changing precision. Computations are performed using systolic array architecture. Fixed point units are converted into floating point units prior to computations. The performance of the results are also studied and analyzed. |
