Design Of Key Components Of Baseband Signal Processing System For Wireless Communication

Wireless communication plays more and more important role in modern society.Compared to the wired communication,wireless communication is more convenient,wider range covering,and we can predict that the applications will be more common in the future.In the wireless communication systems,the baseband signal processing is a very important part,which covers all the signal processing modules from the MAC layer interface to the RF front end.Currently,the baseband signal processing chips also have a growing market demand.Therefore,the study addressing the baseband signal processing is very significant.IEEE802.11 n is a new generation of wireless local area network communication protocol.It has a higher rate than previous generations.It has been widely used in wireless devices.This protocol contains encoding and decoding,modulation and demodulation,digital filtering,MIMO and other algorithms.Based on this protocol,this paper addresses the baseband signal processing algorithm,and implements important algorithm with FPGA.By this method,it can meet the requirements of processing latency,flexibility and scalability.This paper focuses on the encoding,decoding and digital filter technology in the base band signal processing system by learning the theory,and implements them creativity.Convolutional coding is used to ensure the correlation of each code by increasing the redundancy of information,so that the receiver is more likely to recover the transmitted signal.This paper uses the direct structure of shift register and the addition of the specified node,which achieves superior performance compared to the general IP by 40%.Viterbi decoding is a high complexity algorithm,which is the decoding module of the convolutional encoding.By comparing the received sequence with the various possible paths of the encoding trellis,the path with the largest similarity would be found.According to this algorithm,in this paper,we compares accumulated metric value,reserves the surviving paths and surviving bits,when the received signal reaches back depth,we chooses the minimum state and surviving bit and reach back to the depth continually,then produce the decoding output.This paper solves the overflow of accumulated metric value by computing absolute value,which uses less resource compared general method.The submodules of the design mainly contain the branch metric module,add–compare-select module,backtracking module,surviving bit RAM and accumulation path metric RAM.The results show that the designed architecture achieves better performance compared to the common viterbi decoder IP module by 12%.We select FIR filter,whose basic structure is the delay unit and multiplier and adder.The filter transfers and calculates signal sequence to achieve the purpose of filtering high frequency noise.According to multi-rate characteristics,this paper achieves an improvement of the direct implementation of the structure.This architecture reduces the wasted of computation,reduces the number of multipliers,compared with the traditional direct type filter.The improved interpolation filter and decimation filter reduce the using of FPGA resource by 30% and 40%,and achieve 60% and 35% performance improvement.