Design Of Multi-core Processor Based On NoC Architecture

The difficulty of enhancing the chip with single-core CPU's performance only by increasing its own dominant frequency keeps sharply aggravated,the method of multi-core architecture was put forward in this condition.Although multi-core architecture helps solve the problems single-core used to be faced with from a large extent,its communication architecture which relies on bus is bring out new technical bottlenecks with the increase of cores' number.Against that background,the technology named network on chip was come up with to supersede traditional bus for the role of multi-core's new communication architecture,NoC uses Internet's architecture for reference to provide multi-core CPU with lower system delay and less energy consumption,also more flexible expansibility,thus effects a permanent cure.In this paper we chose an applicable topology for the NoC multi-core architecture first,then designed modules of switch network and resource nodes for it,together with its communication protocol.In addition,the classical XY routing algorithm was improved in order to obtain ability to control congests and tolerate the faults between nodes.Finally we realized a 4×4 NoC homogeneous multi-core CPU system based on 2D-Mesh topology on the Altera FPGA hardware platform,with 16 identical Nios? single-core SOPCs as resource nodes respectively.We also accomplished the performance tests of the improved routing algorithm and the NoC multi-core system.According to the results,data package composed of 3 flits with the size of 52 bits each can reach a transmission rate of 214.4kPackets/s on chip,it means that the NoC multi-core system we designed can achieve a normal operation.