Modeling And Implementation Of Dynamic Swappable Pipeline RISC-V Processor

With the development of microelectronics, information, communication and network technology, Internet of Things has been applied in the fields of health care, artificial intelligence,network management, logistics and transportation. In these applications, the collection and processing of information is the basis and key of the Internet of things. The information collection and processing nodes are widely distributed in Internet of things, and not easy to replace the power supply, therefore, low-power information collection and processing chip is the key to ensure the normal work of Internet of Things.This paper proposes a dynamic swappable pipeline processor to balance the requirement of high performance and low power in Internet of Things networking application by analyzing the demand of processor in different application scenarios and researching the low power design technology in high performance processor. First of all, subdivide the pipeline based on the classic pipeline architecture and a seven-stage pipeline architecture is designed with RISC-V instruction set for high-performance mode. Secondly, a simplified structure is implemented by simplifying the seven-stage pipeline architecture to apply it in low power mode. Finally, a switchable-pipeline RIISC-V processor is designed based on above two kinds of structure. In the overall system, these two modes share memory, cache, ALU execution unit and use corresponding software scheduling strategy to complete the data exchange and task switching in program execution. In the whole process of implementation, the system is modeled by SystemC for periodic modeling firstly, then the hardware circuit is implemented with Verilog language,and finally complete the function simulation and corresponding power analysis of the model.Among them, single-core based on high-performance mode has been taped out wilth SMIC 180nm process and has been tested.In this paper, function of the system is simulated by choosing self-built addition, matrix multiplication and standard test program DMIPS, CRC, AES as test vectors, and finish the performance power analysis with HP Labs' McPAT and Synopsys' DC from the system and circuit level respectively. When applied to the Internet of Things, compared to a single high-performance mode processor, the proposed processor architecture in this paper can achieve the design requirements with hardware resources is increased by only 5%, while the system power consumption will decrease by 67.23%. And the longer time proportion that data acquisition stage takes, the effect of the reduction of the system energy consumption is more obvious.