Software And Hardware Combination Of The Mp3 Chip, Low Power Consumption

MP3music compression format is developed for MPEG digital audio compressionstandard, and its advantages have been widely used in the network and a variety ofmultimedia portable system. Now, it still remains a major audio format. MP3player wasa smash hit, for several years in the market test. After an investigation there is aconclusion: good sound quality and long standby MP3player to win the market. Atpresent, the sound quality of MP3players are generally80dB~95dB, almost the same.Then the key is that the standby time, in another word, the low-power SoC (System onChip) within the MP3player.SoC low power technology, from reducing the operating voltage of the system,to improving the analog amplifier power, and then to improving the digital power of thecircuit, the conventional techniques have been exhausted but the power consumptionneeds to be further reduced, only depending on the software and hardware combinationof strategies: to make a fuss in the algorithm layer, analysis and improvement of MP3decoding algorithm to optimize the computation steps, under the premise of ensuringthe sound quality, reduces the computation, reducing the burden of the processor, tocoordinate software and hardware to work effectively to achieve Reduce the objectivesof the work of dynamic power consumption.This article is based on an MP3chip in the market, through a detailed analysis ofthe MP3decoding step, and distribution of power in the statistical decoding process, itsCPU and DSP dual-core architecture has been changed to a single CPU and hardwaredecoding module architecture, and software decoding is instead of hardware decoding.Hardware is responsible for huge computing jobs, to solve the weak matrix operationsof software. In hardware module design, combined with coordinate rotation digitalcalculation (CORDIC), the inverse modified discrete cosine transform (IMDCT) andthe synthesis filter (Synthesis Filter Bank) in the matrix conversion (Matrixing,) areboth optimized, reducing the original at least more than25%of the multiplications andadditions in the algorithm, and designed to cycle hardware module requiring only14Mhz clock frequency for working, greatly reduces the dynamic power of the hardware decoding. A new address bus is imported to optimize the frequency of theaddress flip during memory access, then to reduce long-distance address transmissionpower. Rewrite the C language of control procedures, to optimize the system decodingprocess, and to adjust the clock frequency of each module dynamically. Finally, FPGAverification and EDA tools for digital circuit power estimation, confirme the accuratefunction and lower power consumption after improving. And the chip operating current(digital circuit current and analog circuit current) is reduced from the original18.7mA to13.3mA, reducing digital circuit power up to nearly45%decline, achieving the desiredobjectives.A combination of hardware and software, throughout the whole process of thispaper, the design and verification, this method is an important development direction ofthe chip low-power technology, but also the significance of this study.