High-performance SHA-256 Hardware Circuit Research

With the development of the digital age,digital information poses a huge challenge to information security.As an important means of ensuring information security,encryption algorithms have been widely studied.Among them,the hash security algorithm represented by the SHA-256 algorithm is widely used due to its unidirectional irreversibility,uniform hash value distribution,and resistance to message collisions.Apply to the field of information encryption.However,the hardware implementation of this algorithm has the problem of large power consumption when a large number of continuous data is encrypted,which brings about cost,performance,and security issues.Therefore,it is extremely important to conduct highperformance SHA-256 hardware research.Firstly,the thesis optimizes the circuit performance as the primary indicator.By analyzing the basic algorithm,a two-stage pipeline is used to split the critical path of the data iteration circuit,construct intermediate variables for pre-calculation,and perform delay balance processing on the data expansion circuit to avoid becoming a new key Path;On this basis,accounting for a large proportion of the critical path delay,special multi-input adders are constructed according to the characteristics of the algorithm,and part of the adders are solidified,which greatly reduces the delay of the adder;then under the premise of ensuring performance,continuing to optimize the circuit power consumption as the primary indicator.Through the fully customized dynamic flip-flops and buffers,the circuit's register power consumption is effectively reduced;for the continuous data storage of the data expansion circuit,the phenomenon of redundant power consumption is proposed.REGFILE storage is proposed.The circuit replaces the traditional shift register chain circuit,realizes data access in a fixed period,reduces the related power consumption caused by register redundancy jump,and finally reduces the overall circuit power consumption,and realizes the improvement of the overall circuit energy efficiency.This thesis uses TSMC 7nm process to complete the design of a fully customized cell,and completes the hardware circuit design.The power consumption is reduced by 48.4% and the performance is increased by 93.9% when the performance is increased by 192%.Compared with similar researches,the efficiency is significantly improved.After the back-end layout and routing,through simulation verification,the highest frequency of the SHA-256 hardware circuit designed in this thesis can reach 920 MHz.When the frequency is 800 MHz,the power consumption is 22.2 m W,and the circuit efficiency can reach 36.04 Ghps/W.