Design And Implementation Of High-speed Satellite Communication Modulator-demodulator

With the continuous development of satellite communication technology,high-speed modulation and demodulation technology has been attached far-reaching military significance and high civilian value in order to meet the growing demand for data transmission in satellite communications.In this paper,we have studied deeply the design and implementation of 16 APSK modem which is suitable for satellite communication,which provides the theoretical basis and implementation method for the reliable transmission of high-speed data.The research focuses on the high-order modulation,high-speed parallel architecture,the design of 16 APSK modulator and the design of 16 APSK demodulator.Firstly,the current study status and evolution trend of the satellite communication modem is introduced.Subsequently,the characteristic of nonlinear channel in satellite communication is studied,and the 16 APSK is chosen in satellite communication.The advantages and disadvantages of three existing high-speed parallel processing architectures are compared.This thesis focuses on the analysis of the theoretical basis of the modem including the basic principle,mathematical model and the structure of modulator and demodulator.The key technologies in modem,including shaping filter,carrier recovery,bit synchronization and frequency synthesis is also studied.Secondly,the constellation diagram of 16 APSK is optimized,and the radius ratio of inner and outer circle of 4 +12-ASPK constellation is chosen to be 2.7,which has the best anti-jamming performance.In order to reduce the data processing rate,a complete parallel structure of the modem based on the APRX structure is designed.The key technologies of high speed modem are studied mainly.In modulator part,the parallel shaping filtering with multi-phase structure and the up-conversion technology with parallel NCO are studied.In demodulator part,two kinds of matched filter parallel structures in time domain and frequency domain are studied,and the computational complexity is compared.The Gardner algorithm is compared with leading or lagging gate method,and Gardner bit synchronization loop is studied.An improved combined carrier recovery method is proposed,which has a larger carrier frequency offset acquisition range and a more stable tracking performance.The high speed data interface of is designed,and the offset adjustment technique is studied.Finally,the high-speed 16 APSK modulator and demodulator are designed and implemented on the Xilinx platform.The design method and debugging results of the main function modules in the 16 APSK high-speed modulator and demodulator are described in detail,including the multi-phase parallel shaping filter module and the parallel NCO up-conversion module in 16 APSK modulator,the time domain parallel matching filter module,parallel Gardner bit synchronization module,parallel carrier recovery module in 16 APSK demodulator.Then,the correctness of the module and analyzes the usage of FPGA hardware resources are verified.