Design And Implementation Of Entropy Decoder In VP9

With the rapid development of network communication and digital media,the demand for high-definition video service is getting higher and higher,4K ultra-high-definition video has become the mainstream,thus video decoder chip presents a broad market space and development prospects.VP9 video compression standard is widely favored by the market because of its royalty-free and high compression efficiency advantages.The decoding rate of VP9 entropy decoder determines the decoding rate of VP9 video decoder.Therefore,it is a research hotpot to optimize the hardware structure of VP9 entropy decoder.In this paper,an efficient entropy decoder is designed to meet the requirements of real-time decoding in conjunction with VP9 entropy coding algorithm.The main work includes: the overall hardware architecture of the entropy decoder is built.The entropy decoder is designed by the three-stage pipeline structure.The handshaking signal is guaranteed at all levels to improve the accuracy of the data transmission and improve the system performance.The probability table is divided and reorganized by the method of codeword merging,which improves the efficiency of probability table indexing.A combination logic circuit is used to select the fixed probability value,which avoids the access to the memory and reduces the timing overhead.For the binary arithmetic decoding module,a parallel double bin decoding structure based on guessed execution,which optimizes the critical path of the module from the algorithm level and the circuit level,makes the decoding rate of the entropy decoder to reach 2bin/cycle.The RTL level modeling of VP9 entropy decoder main module is completed and the function simulation is carried out to verify the correctness of the design.The whole entropy decoder was synthesized and verified by TSMC 28 nm process,the results show that the frequency of the entropy decoder is 400 MHz,the total area is 38766.74 um2,the total power consumption is 5.59 mW,and the timing is not violated,which can meet the real-time decoding requirements of 4K@30fps HD video and meet the design requirements.