On-chip Network Mapping Model And Tool Design

With the advance of semiconductor technology, it allows integrated-circuit (IC) designers to integrate a huge number of transistors on a single chip,which provides the advantages and challenges for IC industry itself. System-on-chip (SoC) technology was proposed in the nineties of the 20th century to provide an efficient way to implement the complex electronic systems. Since the internal connections among on-chip multiprocessors became more and more complicated, an effective method called network-on-chip (NoC) was presented to solve these complex on-chip communication issues.This thesis focuses on the mapping problem of NoC, which is one of the key issues for NoC technology. At first, the design flow of NoC based SoC is introduced. Then, based on the typical mapping models and mapping algorithms, a new simple and effective NoC mapping method is proposed in this thesis. Finally, mathematical models of objective functions and constrains are derived for this mapping scheme.According to the proposed mapping scheme, an EDA tool, called GAgui, used for NoC mapping issues is also designed. The advantages, functional levels, design flow and characteristics are introduced in this thesis.In the case study, we takes a MIMO/OFDM receiver of wireless transmission systems as an example to explain how to use the proposed scheme and EDA tool and demonstrate the advantages of the mapping scheme and the efficiency of the tool.The method introduced in this thesis, which is consist of a mapping model, mapping algorithms and mapping tool, could be used for the practical system design and NoC researches.