VLSI Architecture Design Of Transform Quantization And Data Storage Module Based On HEVC

As a new generation of video compression standard,HEVC introduces many new coding technologies based on the mainstream hybrid coding framework,which greatly improved the video coding efficiency,its compression performance has doubled compared to the current widely used H.264/AVC standard,which can better adapt to the encoding and transmission of high-definition,ultra-high-definition video.However,the HEVC standard increases the coding performance while increasing the computational complexity of the encoding,resulting in a dramatic increase in the hardware overhead of the encoder in the implementation process.As the key two aspects of the HEVC standard,DCT transform and quantization are very complex,accounting for a lot of hardware overhead of the whole encoder.Hardware overhead comes from two aspects mainly: one is HEVC support the 32x32 largest size of the TU block division,with the increase of TU size,computational complexity of the DCT transform also increases,leading to the increase of hardware overhead;the second is the increase of TU size allows the storage of intermediate data during the coding process to consume more memory cells,for example,the quantized transform coefficients need to be stored before entropy coding,and the reconstructed pixels caculated from the predictive pixels and the reconstruction residuals also need to be stored.In this paper,based on the coding of 4K and 60 fps high-definition video,a architecture design based on 16 parallelism pipeline is proposed for the DCT transform and quantization in HEVC.The structure design is developed from the following two aspects mainly: First,according to the principle of butterfly transformation,large size DCT transform structure can be multiplexed with smaller size DCT transform structure,and then multiplication can be converted into addition and displacement by using the method of adding trees,while storing the middle of the calculation results by using registers,this design method not only reduces the computational complexity,but also reduces the hardware overhead to a large extent;Second,the DCT transform uses the SRAM instead of register to complete the storage and transpose operation of intermediate data,although the control of SRAM address is more complex than register,this design further reduces the storage hardware overhead.After implementing the hardware architecture design of transformation and quantization,this paper completes the structural optimization design for the storage of data related to transform quantization.The optimization design is proposed from the following three aspects mainly: First,optimizing the storage module between the quantization module and the module which calculating the binary data by using the SRAM-based Ping-Pang storage structure,not only facilitates the calculation of follow-up module,but also reduces the storage overhead;Second,completing the storage structure design between quantization module and CABAC module by using SRAM,avoids the repeated calculation of transform and quantization,and reduces the hardware overhead of entire encoder,while completing the optimization of the storage structure based on the cycles of computing costs;Third,the storage of reconstruction pixel has been simplified by using "L" type storage structure instead of the square storage structure,and this design further reduces the hardware overhead of storage.The results of the experiment show that the DCT transform and quantization hardware structure of 16 parallelism in this paper not only satisfies the speed requirement of processing 4K,60 fps HD video coding,but also reduces about 42% hardware overhead compared with the hardware implementation structure which has the same parallelism.At the same time,the three data storage structures designed in this paper also reduce the storage hardware cost of the whole encoder greatly.