Hardware Design And Implementation Of Intra Prediction,Transform And Quantization In AVS-s Video Encoder

With the development of video technology, video surveillance technology is widely used. AVS-s video coding standard is developed independently by China, to meet the special needs of video surveillance technology. This paper studies the design of intra prediction, quantization and transform modules of video encoder based on AVS-s video standard.According to the AVS-s video coding standard and design objectives, this paper optimizes the algorithm and hardware structure of intra prediction module, quantization module and transform module. For each module design the hardware structure and complete the RTL coding. Considered the chip coding speed and chip area and hardware complexity, this paper optimizes the algorithm of each module when designing the hardware structure. Fully considered the hardware complexity of intra prediction module while designing the hardware of intra predition, designs a common intra-prediction mode circuit for the same prediction algorithm. Analyzed the complexity of Plane prediction mode, this paper optimizes the circuit design of Plane mode and designs a hardware structure just for Plane mode. Achieved8pixels paralled processing, and improved the speed of the intra prediction. Using butterfly algorithm designs the hardware for the integer DCT encoding module. For the characteristics of integer DCT transform, designs a simple circuit structure of transposition and4-stage pipeline to process the coding data. Taking into consideration of the complexity of the circuit and processing speed of coding data.After completing RTL design of intra prediction, DCT and quantization module, this paper carries out functional simulation for each modules with VCS of Synopsy. Compared the module results with the output of reference model of AVS-s standard, verifies the correctness of design. After the functional verification, this paper synthesizes the design with Design Compiler tool of synopsys.This paper uses TSMC0.13um CMOS technology to synthesis the circuit. The synthesis results of intra prediction module shows that the area of the module is 123664.313280um2and the dynamic power of the module is24.4619mW. The synthesis results of DCT and Quantization module shows that the area of the module is102072.521707um2and the dynamic power of the module is1.0283mW.