The FPGA Implementation Of Channel Estimation And Equalization Of Chinese DTTB System

Chinese Digital Television Terrestrial Broadcasting (DTTB) standard (GB20600-2006) was published in August 30^th of 2006, and came into force in August 1^st of 2007.This paper focuses on the FPGA (Field Programmable Gate Array) implementation of the channel estimation and equalization for this standard. To finish this task, this paper gives an introduction to this standard and its frame structure which bases on the TDS-OFDM technology. In TDS-OFDM (Time Domain Synchronous orthogonal Frequency Division Multiplexing) system, pseudo-random noise (PN) sequence is used as the guard interval. This interval helps the synchronization and channel estimation in the DTTB receiver. But it destroys the cyclic-convolution structure of the received data, so before the frequency-domain equalization, cyclic-convolution rebuild must be performed. This is the theoretical basis of this paper. And the main work of this paper includes:1 To study the channel estimation algorithm, give a method to erase the interference of PN auto-correlation result, which can easily be implemented in the FPGA.2 To study the channel equalization algorithm, this consists of cyclic-convolution and frequency equalization.3 To implement these algorithms on FPGA. PN auto-correlation structure is detailed studied to optimize the resources usage in this design. Cyclic-convolution module is well designed to manage the complex timing-logic. And CORDIC algorithm is used to implement the complex divider used in the frequency-domain equalizer. The content of this paper includes algorithm study, simulation and implementation. And the key work is to translate the mathematical algorithm to the FPGA design structure.The implementation in this paper works well with other modules in the system, when it is downloaded into the FPGA platform. And we get the desired result.