Novel Structure Design And Application Research On Tunnel Field-Effect Transistor

With the continuous development of semiconductor technology,the size of Met-al-Oxide-Semiconductor Field Effect Transistor?MOSFET?,the core component of elec-tronic products,is scaled down continually.But the operating voltage of the MOSFET cannot be decreased with the shrink of the process,which makes the power consumption a major challenge for MOSFETs.The working mechanism of hot electrons emission results in that subthreshold swing?SS?of MOSFET cannot be lower than 60mV/dec.The higher subthreshold current?off-state leakage current?is the main source of static power con-sumption.At present,the tunneling FET?TFET?proposed by researchers is an effective low power device.The conduction mechanism of band–to-band tunneling breaks the limi-tation of 60mV/dec SS.And the extremely low off-state leakage current greatly reduces the power consumption of device.The traditional planar TFET is based on the tunneling diode governed by gate.Due to the indirect and higher bandgap,the low on-state current restrains the large-scale application of planar silicon-based TFET.Furthermore,the complex heavy doping process is also one of the challenges that TFETs face.In recent years,many researchers have designed some novel structures,such as the heterojunction TFET,U-shaped channel TFET?UTFET?,dopingless TFET,etc.In the heterojunction TFETs,applying the heterojunction between source and channel can effectively decrease the tunneling barrier width so that the BTBT generation rate is enhanced.The UTFET utilizes the recessed channel to achieve the larger line-tunneling area,which is helpful for the promotion of on-state current.The dopingless TFET mainly solves the problem of heavy doping process.In the dopingless TFETs,all the regions use the intrinsic materials,and the source and drain regions are mainly formed by choosing the appropriate work function of metal.Although these novel TFETs have solved some problems,their performances still have more space to be improved.As a result,it is necessary to further research the novel structures of TFET.Based on the UTFET and dopingless TFET,this dissertation proposes two novel structures of TFET—T-shaped gate TFET?TGTFET?and line-tunneling dopingless TFET?LT_DLTFET?.TGTFET mainly improves the structure of UTFET to greatly enhance the on-state current.In the LT_DLTFET,the line-tunneling is applied into doping-less TFET to elevate the on-state current.In addition,the applications of TFETs to dynam-ic random access memory?DRAM?and digital standard unit circuits are also be studied.The specific research contents are as follows:1.In the TGTFET,the drain is placed at the bottom of channel,and the sources are placed on the two sides of gate.The vertical line-tunneling area of TGTFET is twice that of UT-FET.Besides,the T-shaped makes the top sources create the line-tunneling.Comparing to UTFET,the line-tunneling area of TGTFET is maximized keeping the unchanged area of device,which extremely enhances the on-state current.Furthermore,inserting the pockets into soureces reduces the line tunneling barrier width,which further improves the on-state current of TGTFET.In addition to using silicon in this structure,Ge/SiGe heterojunction engineering is also adopted,namely,the sources,pockets and channel/drain use the germa-nium,SiGe and silicon,respectively.Comparing to silicon-based TGTFET,the on-state current of heterojunction TGTFET is increased by two orders of magnitude.By optimizing device parameters of TGTFET with the Sentaurus TCAD tool,the performance of TGT-FET is improved greatly.The simulation results show that the on-state?Vg=Vd=1V?cur-rents of silicon-based TGTFET and heterojunction TGTFET are 9.6×10^-6A/?m and1.9×10^-3A/?m,average SS are 32.42mV/dec and 38.43mV/dec,cut-off frequency are3.82GHz and 313.27GHz,maximum gain band product are 7.56GHz and 620.22GHz,re-spectively.2.The traditional dual-gate dopingless TFET can only create the point-tunneling.The germanium-based dual-gate LT_DLTFET is designed in this dissertation.By skillfully choosing work functions of top and back gates,the line-tunneling from the channel bottom to channel top is created in LT_DLTFET.And the line-tunneling area strongly depends on the overlapped area between top gate and back gate.When the gate voltage is higher,the tunneling rate of point-tunneling is higher than that of line-tunneling.Therefore,the line-tunneling plays the important role under the condition of low gate voltage.The several device parameters of LT_DLTFET influence the on-state and off-state currents.Especially,the work functions of top and back gates affect the line-tunneling barrier width in the channle region.Keeping the same device parameters of the traditional dopingless TFET and LT_DLTFET,the work functions of top and back gates are adjusted to 3.9eV and 4.6eV.When the gate voltage is 0.8V,the drain currents of dopingless TFET and LT_DLTFET are4.2×10^-6A/?m and 1.3×10^-5A/?m,respectivley.This indicates that line-tunnling dose improve the on-state current of dopinglss TFET.3.Applying TFET to DRAM is helpful for the reduction of reading“0”current.The read-ing and writing operations of dual-gate TFET DRAM?DGTFET DRAM?rely on the BTBT near the source and drain sides,respectively.Because the tunneling current is gov-erned by the gate voltage,it is indispensable to optimize the programming voltage of DGTFET DRAM to improve its performance.What's more,the spacer dielectrics of DGTFET also have effects on the reading and writing currents of DGTFET DRAM.The influences of different spacer dielectrics and programming voltages on reading and writing currents are also analyzed in this dissertation.On the basis of low reading“0”current and high reading“1”current,the optimal spacer dielectric and programming voltage is ob-tained.The DGTFET DRAM obtains the better performance after optimizations of pro-gramming voltages and spacer engineering.The reading“0”current is low to 1.40×10^-14A/?m,and the retention time can reach up to 2s,which implies that DGTFET can reduces the dynamic refresh rate and static power in application of DRAM.4.Finally,the applications of TFET to digital standard unit circuits are also studied in this dissertation.Using the existing Verilog-A models of InAs TFET and AlGaSb/InAs TFET,the noise margin,delay and static power of inverter,combinational logic circuits and static random access memory?SRAM?are also calculated.The results show that InAs TFET can reduce the noise margin of unit circuits.AlGaSb/InAs TFET can reduce the static power of unit circuits,which is related to lower off-sate leakage current of AlGaSb/InAs TFET.Due to the asymmetrical doping of source and drain of TFET,there are two circuit structures of TFET SRAM—source inward connection SRAM and source outward connection SRAM.The different circuit structures of SRAM mainly influence the noise margin instead of static power.The noise margins of inward connection and source outward connection SRAMs are 109.57mV and 173mV,respectively.The static powers of these two SRAMs are 1.88nW?14.03pW,respectively.This is much lower than static power of MOSFET SRAM.It fully demonstrates the application potential of TFET to low power integrated circuits.