Integration Of Tunneling Field Effect Transistor

As the feature size of semiconductor devices continues to shrink in proportion,the size of the chip made of it is also continuously reduced,but with it is a sharp increase in power consumption density.However,traditional MOSFET devices have a theoretical limit of sub-threshold slope(60m V/dec)at room temperature due to their conduction mechanism,which makes it impossible for chips based on MOSFET devices to continuously reduce the power supply voltage to reduce the power consumption of the chip.Therefore,the research of new devices with low sub-threshold slopes and ultra-low power consumption is very important.Among them,tunneling field effect transistors have received wide attention from domestic and foreign researchers in recent years due to their extremely low off-state current,ultra-steep sub-threshold slope SS,and compatibility with CMOS technology.However,when TFET devices are integrated,due to the structural characteristics of the TFET itself,both NTFET and PTFET have P-type doped regions.These P-type doped regions will be connected through the P-type substrate.When there is a voltage between these doped regions In case of difference,substrate leakage will occur.When the substrate leakage current far exceeds the extremely low off-state current of the TFET,it will conceal the advantages of the low off-state current and low static power consumption of the TFET.Secondly,in terms of device performance,TFET also has certain problems.For example,the problem of small on-state current I_ONdue to the small tunneling probability,etc.,so the research on TFET performance is also very necessary.In response to these two issues,this thesis has done the following two types of research:First,given the above-mentioned substrate leakage problem,two isolation plans,Nwell-Psub and Nwell-Pwell,are used for leakage isolation.In this paper,a simplified three-dimensional simulation model composed of NTFET and PTFET was first established on Sentaurus TCAD software,and the leakage problem caused by substrate connectivity was verified without isolation;after that,two leakage isolation plans were added for a lot of simulation work.Theoretical analysis and simulation of two parameters that have a greater impact on the isolation leakage effect:Nwell spacing and concentration,the following conclusions are drawn through simulation:as the Nwell spacing increases,the leakage between the P-type doped regions Ipp and N-type The leakage Inn between the doped regions will decrease;as the Nwell concentration decreases,the Ipp will increase,and the Inn will decrease;compared to the Nwell-Psub plan,the Nwell-Pwell plan has better performance.Finally,a test plan was formulated.A large number of tests were performed on the Agilent1500 probe station for the inverters that were taped out according to the substrate leakage isolation plan.After sorting and analyzing the data,the test results were compared with the simulation results to verify the effectiveness of the isolation plan.Second,in the performance optimization of TFET devices,a tape-out experiment will be carried out in the subsequent group,and the relevant parameter values??need to be simulated first.In this paper,the energy and measurement of the source area LDD injection are simulated accordingly.Because of the process sequence problem,the source region LDD implanted after the thin sidewalls have a certain distance from the left side of the gate,and it needs to diffuse to form a steep junction with the channel.Therefore,it is necessary to reasonably control the source region LDD implantation dose and energy.In this regard,a two-dimensional simulation model was established on the Sentaurus TCAD simulation software to simulate the effect of different parameter conditions on the performance of the device.By comparing the transfer characteristic curve of the device,the value of the source area LDD injection energy and the dose was determined for subsequent tape-out.Provide a reference for the setting of TFET device parameters.