The Design Of Frequency Synthesizer In CMOS Technology

Most synthesizers employ "phase-locking" to achieve high frequency accuracy.The phase-locked loop(PLL)principle operation is based on phase comparison to realize"frequency-locking" while the operation of the frequency-locked loop is based on frequency comparison of a reference and feed'back signals.In this paper,the mainstream systems of PLL and FLL are summarized and a fully integrated frequency synthesizer using frequency-locked loop(FLL)is designed,mainly including frequency-to-voltage converter(FVC),operational amplifier(OPA),voltage-controlled oscillator(VCO)and divider.The chip is designed and implemented in GSMC 130nm CMOS technology.The core area of the circuit is about 470?m×350?m.Post-layout simulation results show the center frequency of the output signal is about 1GHz with a locking time of 1.1 ?s.Measurement results show the proposed FLL works well with at 651 MHz with the phase noise of-124dBc/Hz@1MHz while consuming 26.4mW with a 1.2V power supply.The output frequency of PLL is determined by the oscillator.Because of the off-chip inductor in VCO,the measurement result of the output frequency is lower than the simulation result.To measure the characterization of an integrated resonator easily and efficiently,the fifth chapter of this paper presents a bridged contactless measurement technique which can measure the resonant frequency and quality factor of a fully-integrated powered off LC oscillator.The efficiency of the method has been validated using commercial electronic design automation(EDA)software.The simulated results and the calculated results agree considerably well,which suggests the feasibility of using this technique in potential contactless measurement.At last,a conclusion of the work of this paper has been given,and a prospect of the next research in the future has been analyzed.