| FPGAs have witnessed an increased use of dedicated communication interfaces. With their increased use, it is becoming critical to test and properly characterize all such interfaces. Bit error rate (BER) characteristic is one of the basic measures of the performance of any digital communication system. Traditionally, BER is evaluated using Monte-Carlo simulations, which are very time-consuming. Though there are some BER test products, none of them includes channel emulator. To overcome these problems, this thesis presents a scheme for BER testing in FPGAs, with a few orders of magnitude speedup compared to Monte-Carlo method. This scheme consists of two intellectual property (IP) cores: the BER tester (BERT) core and the additive white Gaussian noise (AWGN) generator core. Two challenging testing cases are successfully conducted using the testing scheme. We demonstrate through case studies that the proposed BER testing solution exhibits advantages in speed and cost compared with the existing solutions. |
