Performance Evaluation And Analysis Of SoC Based On FlexNoC

In the traditional So C design,the bus-based IP core interconnection architecture faces many performance limitations.Network on Chip,as a novel on-chip communication solution,can effectively solve the bottleneck problem of large-scale So Cs.In order to obtain high-speed communication processing capability so as to meet the practical application requirements,and achieve high-performance So C chip design and verification,we must establish a systematic and efficient performance evaluation methods for No C architecture.Due to the lack of reliable hardware/software co-verification and architecture evaluation methods,system architects will be subject to certain obstacles when design system-level chips.Unlike the traditional RTL simulation environment,the Flex No C platform in this paper adopts the System C transaction level modeling technology to analyze the No C test model quickly.It can give accurate and reliable performance evaluation results to help the developer to carry out system-level design.Therefore,hardware system performance verification can be achieved in the early stages of chip architecture design to reduce development costs,and the development period is significantly shortened.This paper evaluates and analyzes the performance of the No C architecture in an Intel chip based on the Flex No C design and verification environment.Firstly,introduce the design method and key technology in No C research,and analyze the performance advantages of No C technology as well as the related theory of improving performance.Then this paper explains the design framework of Flex No C in detail,and summarized the influencing factors and optimization strategies of No C performance by analyzing its topology and various hardware transport units.On this basis,take the corresponding flow control of each IP module in the interconnection network by the Quality of Service mechanism to meet the performance requirement in the system design.Finally,this paper proposes the overall flow scheme of performance evaluation using Flex No C,and prepares the test cases according to the specific application scenarios.We can find the performance weakness through the data analysis,and adjust the parameters on the related No C path with compromises between bandwidth,latency,area and other aspects.The final simulation results achieve the expected indicators.The research work of this paper mainly includes the following aspects:1)Introduce the basic concept of No C performance design and verification,then summarize its advantages and technical issues to be solved.Concentrating on the Flex No C environment,propose the specific workflow of the performance evaluation and direction for performance optimization.2)Create and modify the topology of the chip system on Flex No C.Configure the hardware transport units such as serialization adapter,FIFO or rate adapter for the path that does not meet the performance requirements,and set the Quality of Service mode in consideration of the compromise between performance and area.3)Determine the system performance indicators for the typical application scenarios,and design the test cases.Through sorting,analysis and feedback of the data,the simulation results show that the No C performance in the So C is identical with expectation,and efficient Flex No C platform is appropriate for early design and performance verification of the chip architecture.