Low-power On-Chip Networks In High-Performance Multi-Core Processors

Network-on-Chip(No C) is a very important component of the high-performance processor. It deals with message transmission between cores or caches. As the number of on-chip elements increases rapidly, the performance of No C has more impact on the performance of the whole processor. Traditional interconnection network has suffered from low bandwidth, high latency and high power consumption. The power consumed by No C can be a significant part of the entire chip’s power. Therefore, low-power No C design has become an important research problem. The thesis explores and studies the architectures of low-power photonic No C, the analysis of worst-case backlog bound in traditional No C and how to apply low-power techniques to No C design. The main contributions are summarized as follows.(1) A Hierarchical Butterfly-based Low-Power Photonic Network-on-ChipAs silicon-based photonic technology develops, photonic Network-on-Chip has attracted much attention for its low-power feature. Different from the traditional metallic interconnection, photonic No C uses light to transmit messages, which can save much power consumption. Photonic on-chip networks with advanced CMOS-compatible photonic devices, brings a bright future. In photonic Network-on-Chip, the data transmission method is different from that in electronic network. The message transmitted has to be modulated to light signal before prorogating in waveguide. The signal cannot be buffered or computed during transmission procedure. How to improve the power efficiency of photonic network-on-chip is an interesting and challenging research problem. Now, all of the proposed methods use a lot of photonic components to build the architectures,which introduces high insertion loss, high transmission power and high area occupation.The thesis presents a hierarchical butterfly-based photonic Network-on-Chip(HBPNo C). The proposed network leverages the electronic and photonic technology to improve on-chip network performance. HBPNo C uses hierarchical architecture for packet switching in intra-cluster networks and circuit switching in the inter-cluster network. The inter-cluster network is a scalable butterfly-based one, called butterfly-based photonic Network-on-Chip(BPNo C). The reason why our BPNo C can achieve high scalability is twofold. First, different from previous photonic No Cs, BPNo C just use one basic photonic switching element(PSE2x2), to build each hybrid router. Second, as we know, thebutterfly network and the PSE2x2 are both unidirectional. It is a natural way to insert the PSE2x2 into the butterfly-based photonic network. Thus the photonic transmission cost(including power consumption, optical loss and area) can be significantly reduced.BPNo C is also a hierarchical network with an optical sub-network and an electrical subnetwork. Optical sub-network with a load-balanced routing algorithm use circuit-based switching to transmit data packets, while the electronic sub-network with improved turnaround algorithm is based on packet-switching for control and data packet transmission.The most important feature of the proposed HBPNo C network is that HBPNo C uses hierarchical architecture for packet switching in intra-cluster networks and circuit switching in the inter-cluster network. A butterfly structure, comprised of 2x2 photonic switching elements(PSE), is used for inter-cluster communication. To improve performance and reduce power consumption, the PE router directly forwards intra-cluster messages to their destinations, with utilizing a local electronic switching fabric. The simulation results show that our proposed network has very good performance with low power consumption and low optical loss.(2) Software-Defined Low-Power Photonic Network-on-ChipNow energy efficiency is becoming the most critical design facet for the scaling of Network-on-Chip(No C). Different from electronic network, photonic Network-on-Chip offers natural solutions to reduce energy consumption. However, the proposed photonic networks use distributed method to set up photonic paths, which means that each photonic switch has to be controlled by an electronic router. Such method leads to high power consumption and low resource utilization.The thesis proposes an energy-efficient Software-Defined Photonic Network-on-Chip(SD-PNo C) architecture. The proposed on-chip network utilizes a hybrid architecture,which is comprised of an optical transmission network and an electronic control network.The most important feature of our proposed network is that electronic network uses just one central controller to process and forward control messages. Thus these control messages will not suffer from high hop count to reach destination node. Central controller holds a photonic switching element(PSE) state table and controls all PSEs’ switch on/off. When a new control message arrives, it sets up or tears down an optical link quickly,according to the information carried by the message. The simulation results show that on average our proposed network can reduce at least half of network energy consumption,while keeping low transmission latency.(3) Analysis of worst-case backlog bounds for Networks-on-ChipIn networks-on-chips(No Cs), the power consumed by router buffers can be a significant part of the entire router’s power. While the performance is satisfied, how to reduce the buffer size is a challenging and important problem. Analyzing the worst-case backlog bounds of routers is very important to solve this problem.The thesis proposes a method called Di GB(DIrected-contention-Graph-based Backlog bound derivation) to analyze worst-case backlog bounds. For primitive scenarios, we propose analytical models for backlog bound derivation. For complex scenarios, we first construct a directed-contention-graph(DCG) to analyze the relationships among traffic flows. Then, we use the Breadth-First-Search strategy to traverse the DCG so that complex scenarios can be divided into primitive scenarios. Finally we compute the worst-case backlog bounds of each router. To illustrate this method, we present the derivation of closed-form formulas to compute the worst-case backlog bounds under all-to-one gather communication. The experimental results show that our method can achieve correct and tight worst-case backlog bounds.(4) Designing Voltage-Frequency Island Aware Power-Efficient No C through Slack OptimizationIn network-on-chips(No Cs), power consumption has become the main design constraint. How to reduce the power consumption of routers has become a very important problem. The thesis proposes a power-efficient network calculus-based(PNC) method to minimize the power consumption of No C. Based on the slack that a packet can be further delayed in the network without violating its deadline, the PNC method uses power-gating technique to reduce the active buffer size and uses voltage-frequency scaling technique to reduce the voltage-frequency of each voltage-frequency island. With less active buffer units and lower voltage-frequency, the power consumption of No C is reduced. Experimental results show that the PNC method can save at most sixty-nine percentage of the total power consumption.In summary, the thesis investigates several important problems in the research of lowpower network-on-chips. It has significant academic and practical values in promoting the advancement of research in low-power network-on-chip.