HLS Design For Rough Mode Decision Of Intra Prediction In HEVC

With the development of information technology,the mainstream video gradually becomes high-definition and ultra-high definition video.H.264/AVC compression standards have been difficult to meet the needs of high-resolution video real-time transmission.2013 JCT-CV proposed a new generation of video compression standard HEVC.Its purpose is to improve the compression efficiency of video and support low-bandwidth networks.Compared with H.264/AVC,HEVC’s compression efficiency has nearly doubled.Increasing the compression efficiency also increases the complexity of the algorithm Intra prediction is an important part of HEVC,its complexity mainly comes from two aspects: First,compared with H.264/AVC,the prediction mode of HEVC increases from 9 up to 35.Second,HEVC employ 5 kinds of prediction unit size,including 4×4,8×8,16×16,32×32 and 64×64.Compared with the general processor,the FPGA has a great advantage in the processing speed of the data,so the hardware implementation of the intra prediction is becoming the focus of people’s research.In order to shorten the hardware development cycle,Xilinx company introduced the high level synthesis tool Vivado-HLS,which can use software code through the tools directly describe the hardware design for RTL-level comprehensive simulation verification and implementation.In order to improve the throughput of the rough mode decision(RMD)of intra prediction,this paper designs the pipeline and parallel structure suitable for hardware implementation based on carefully studying of the HEVC standard and the intra prediction algorithm,and achieved in the Vivado-HLS tool.The main work of this paper is:1.A multi-level pipeline the RMD of intra prediction architecture is proposed.We divide RMD of intra prediction into three sub modules including reference point selection module,PE module and SATD module.We design a 8×8 calculation unit architecture,which supports eight prediction point in parallel within the mode and seven mode in parallel on mode level.Reference point selection module uses a lookup table to select the reference points for each prediction point,reducing computational complexity.The SATD module uses the ping-pong way to store the results of 1-D horizontal Hadamard.We establish multi-level pipeline between the modules,and improve the RMD moudle of the intra prediction data throughput.2.Implementation of the RMD moudle hardware structure,which meets the expected throughput with HLS Tools is finished.We implemented reference point selection module,PE module and SATD module and optimized by using HLS tool respectively.Through adding directive partition the array map as registers,and through adding directive unroll the sequential execution map as parallel processing to implement the parallel calculation of prediction points,which shorten the processing delay.Finally,we uses the HLS tool for RTL simulation to verify the correctness of the structure.In this paper,we proposed a multi-level pipelining hardware architecture for RMD moudle and implemented by Vivado-HLS tool.The experimental results show that the architecture can support 1080p@38fps real time encoding at a frequency of 209.58 MHz,achieving the desired goal.The RMD module architecture proposed in this paper has a low algorithm complexity,which can achieve a higher throughput In the FPGA platform.