| The research and implementation of wireless communication system in harsh environment is always a difficult problem in the field of communication. SC-FDE MIMO technology has been applied to the very low SNR communication system, which greatly improved the performance of the communication system due to its obvious ability of anti-fading. Synchronous technology, as a key technology in wireless communication system, can directly affect the performance of the communication system, especially the communication system under the low SNR. In addition, the synchronization technology under the ultra-low SNR has many problems of hardware resource consumption in engineering implementation. Therefore, it is significant to study the synchronization technology of ultra-low SNR and the implementation of FPGA.This thesis mainly studies the fast and accurate synchronization technology in MIMO SC-FDE system with ultra-low SNR, and presents two improved schemes for the problem of hardware resource utilization.And implements Synchronization algorithm based on matched filter on FPGA. The main work is as follows:(1) We study the single carrier frequency domain equalization system and MIMO. The principle of synchronous acquisition and synchronous tracking is studied, and the synchronization training sequence is studied.The characteristics and generation methods of the training sequence are analyzed.(2) According to the -20db and -40db two kinds of very low SNR environment, combined with the system's overall scheme, we present the synchronization scheme. Then, the improved synchronization scheme is proposed to solve the problem of resource-intensive. The program uses the Burst structure of the FFT to carry out the relevant calculation and reuse the FFT, the use of hardware resources reduced by half. In addition,aiming at the problem that the improved scheme does not apply to the-20db SNR system, a synchronization scheme based on the matched filter is proposed. The number of matched filter taps is only 0.56% of the traditional matched filter, which can effectively reduce the resource usage of the synchronization scheme.(3) Based on the Xilinx chip, we implement the synchronization scheme based on novel matched filter. According to the specific function of the module to complete the FPGA timing design, code preparation and function of the module simulation, and complete performance debugging.The synchronization scheme and FPGA implementation studied in this thesis have verified their performance and program robustness through the laboratory and field testing of the actual communication system, and the result is good. |
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