Research And Realization Of If Digitization Spread Spectrum Receiver

As one of the leading and competitive modern communication technologies, spread spectrum communication has shown its great marketing potential. Its main advantages includes: strong anti-interference, code division multiple access(CDMA), difficult to capture with strong security, etc. This thesis revolves around the concept of completing data demodulation, and mainly concentrates on the researches into the areas of digital down conversion, acquisition and tracking of PN code, bit synchronization, carrier acquisition and tracking, data demodulation, etc. Synchronizing technology is a key for direct sequence spread spectrum(DSSS) system, and the quality of system performance directly relates to the quality of Synchronicity. In addition, how this worked out will also be explained. The scheme of digital IF receiver is raised based on the thought of soft-defined radio(SDR), as well as the analysis on environmental influence on high dynamic condition. The feasibility of this proposal will be verified by emulation of both software and hardware.This thesis gives the fundamental principles and features of direct sequence spread spectrum(DSSS) system in details. It also briefly introduces some technologies which are widely adopted in spread spectrum communication, such as digital phase-locked loop(PLL) and matched filter(MF). It will provide theories to support the design of the system. By studying the theory and practice of band-pass sampling, spectrum shifting and digital orthogonal down convert included in band-pass sampling can be combined, hence to achieve the transforming from IF to base-band.For the case of based PN code repeating array, this system uses a method of phase difference to implementing bit synchronization. A code acquisition program based on the matched filter is adopted ,which is more shorten time compared to the traditional PN code acquisition based on sliding correlation, and it meets the needs of rapid capture of the system. For the case of large frequency offset, high dynamic environment, the system use a kind of synchronization strategy to gradually narrow the frequency offset range. At first, it narrows the frequency offset to the range which frequency-locked loop(FLL) normal operation in, by time-frequency two-dimensional searching, and then activate the FLL. When the frequency offset is narrowed in a certain range, the system start the phase-locked loop(PLL), to tracking the residual frequency offset accurate. FLL and PLL extract phase by CORDIC algorithm, and adopt 21-grade pipeline structure, ensuring high extraction accuracy and reducing the circuit delay effectively. Analysis on how carrier frequency bias and phase bias influence the system performance is achieved by the Matlab emulation. Verilog HDL is used for hardware programming, and use ModelSim to carry out the emulation and analysis on the overall performance of receiver system plan. The final test will be carried out on hardware platform, and the test result shows that the system is running smoothly and meets the designing needs.