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Research On Transmitting Architecture Of MIMO-SCFDE System And FPGA Implementation

Posted on:2018-06-25Degree:MasterType:Thesis
Country:ChinaCandidate:S HongFull Text:PDF
GTID:2348330518496833Subject:Electronics and Communications Engineering
Abstract/Summary:PDF Full Text Request
In wideband communication, Single Carrier Frequency Domain Equalization (SCFDE) technology can effectively combat inter-symbol interference created by channel frequency selective fading, MIMO technology can effectively increase the communication performance under multi-path interference without increasing the transmission power and bandwidth. On this background, this paper researched the advantages and disadvantages of MIMO and SCFDE technologies, and proposes a design.scheme of MIMO-SCFDE system based on the application of ultra-low SNR,and focuses on the analysis and research of the Design and Implementation of Transmitter.Specifically, the transmitter designed in this paper includes data acquisition, turbo coding, rate matching, QPSK mapping, space-time block coding, framing, RRC shaping filtering, IF modulation, DA and so on. The,frame length is 20ms, Some of the key technologies are:(1) In order to adapt to long-distance communication and ensure the work of ultra-low signal to noise ratio, the scheme adopts CCSDS standard 1/6 bit rate Turbo code and high repetition code cascade to obtain high coding gain, Error correction capability;(2) In order to ensure the stability of the system in the long-distance scattering channel, Alamouti space-time coding is adopted in this paper,which can improve the system reliability by using the space-time diversity gain in order to combat fading.(3) In order to guarantee the performance of synchronization and channel estimation under low input signal-to-noise ratio (SNR),we design a 2/3ms full-bandwidth long header and pilot to obtain sufficient spreading gain.(4) In this paper, 68-order FIR root raised cosine filter is used to Reduce the sampling error rate.In hardware implementation, this paper use ISE and Verilog HDL, and the FPGA chip used in baseband signal processing part is Xilinx Virtex-6 series, and the working clock of the system is 100M. Taking into account effective data processing and hardware resources, this design from data acquisition to DA use parallel flow processing technology.All the design of the program have been rigorously tested indoor and outdoor, in -25dB signal to noise ratio can still be a long time under the stable work, fully validated the correctness of this design.
Keywords/Search Tags:Low SNR, MIMO-SCFDE System, Transmitter, FPGA
PDF Full Text Request
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