Low-voltage Oxide-based Electric-double-layer Thin-film Transistors On Paper Substrates

In the recent years, paper thin film transistors （TFT） have attracted more andmore interest, because of low cost, renewable, portable and mass production, they arevery potential in the areas of electric paper, product tags, flexible displays and etc.Nowadays, the research about conventional paper TFTs are delayed by the roughnesssurface of paper, process temperature and other difficulties. In the last papers, theoperating voltage of the paper TFTs, more than10V, is disadvantage in theapplications. In this work, we report some solutions to these problems as follows.（1） The microporous SiO₂deposited by plasma enhanced chemical vapordeposition （PECVD） exhibited electric-double-layer （EDL） effect, the physicalthickness of such thin film is4⁸μm, but the equivalent thickness is only¹nm, thespecific capacitance of such dielectric is more than1.0μF/cm². To enhance the EDLeffect, the samples were processed in solutions, and Ca²⁺、K⁺、Na⁺are diffused into themicroporous SiO₂dielectric, the EDL effect is enhanced, the field-effect mobility,subthreshold slope, current on-off ratio, and operating voltage are optimized. The TFTsgated by SiO₂treated by Ca²⁺exhibited specific capacitance of4.2μF/cm²,field-effect mobility of13cm²/Vs, current on-off ratio of1.0×10⁶, subthreshold slopeof80mV/decade. The TFTs gated by SiO₂treated by Na+exhibited specificcapacitance of4.7μF/cm², field-effect mobility of42.8cm²/Vs, current on-off ratio of>1.0×10⁶, subthreshold slope of90mV/decade.（2） We didn’t only study the inorganic materials to be used as dielectrics, organicmaterials are also suitable to be used as dielectrics. Chitosan fabricated by sol-gelexhibited good EDL effect, too. Such materials have a simple fabrication process, itscost is low, it is innocuous and unpoisonous and suitable to mass production. Thechitosan film fabricated by spin-coating exhibited smooth surface, clear film layer andgood adhisiveness with the substrate, with a high specific capacitance of more than1.0μF/cm². To improve the performance of TFTs, stacked SiO₂/chitosan is used to bedielectric, such TFTs have a high field-effect mobility of7.8cm²/Vs, current on-offratio of7.8×105, subthreshold slope of100mV/decade.（3） Many research groups pay attention to the surface roughness of paper, some ofthem reported that spin-coating organic materials could be useful to decrease theroughness of the paper surface. Our group optimized the surface roughness of paper with SiO₂, SiN deposited by PECVD, and TFTs on such SiO₂-coated paper substrateexhibited better performance. This fabrication process has advantages of massproduction, low cost and controllable. Such TFTs exhibited field-effect mobility of14.6cm²/Vs, current on-off ratio of1.5×10⁶, subthreshold slope of100mV/decade.（4） Because the distance between the mask and the sample, diffraction is occurredwhen channel layer is deposited. So, we fabricated self-assembled TFT based on suchdiffraction phenomenon, the process is more simple, the cost is lower and theperformance of TFTs are enhanced. Current on-off ratio is107, subthreshold slope is70mV/decade, the operating voltage is <1.5V. Self-assembled channel decrease theprocess of TFT fabrication, which has high research and application value in low-costand high performance electric products.（5） Based on the self-assembled channel process, our group has fabricatedin-plane gate and dual-in-plane gate TFT. Such TFT exhibited good performances,subthreshold slope is80mV/decade, current on-off ratio is4×10⁶, field-effect mobilityis10cm²/Vs. When the applied voltage of the second gate decrease from2.0V to-2.0V, the subthreshold voltage of such TFT increase from-0.14V to1.15V. When pulsevoltages are applied on both in-plane gates, the output current exhibited OR-gate logicfunction. Which is potential in electric-circuit applications.（6） By further studying the self-assembled process, we found that junctionlessTFT could be fabricated when the thickness of electrode layer is decreased properly,the source/drain electrodes and channel layer of such TFT have the same materials andsizes. Such junctionless TFTs exhibited current on-off ratio of5.8×10⁶, subthresholdslope of0.12V/decade. Like conventional TFTs, such TFTs are also suitable toin-plane gate and dual-in-plane gate process. When the applied voltage of the secondgate decrease from2.0V to-2.0V, the subthreshold voltage of such TFT increase from-0.53V to0.97V. When pulse voltages are applied on both in-plane gates, the outputcurrent exhibited AND-gate logic function.