A Low Power Consumption ADC Applied To SEMG Signal Processing

There is a high demand for analog-to digital converter(ADCs)in the processing circuit of sEMG,which can convert analog signals into digital signals.And in some special application fields,ADC must have medium resolution and medium speed and low power consumption.Besides,it can be achieved in CMOS process easily.Successive Approximation Register Analog-to-Digital Converter(SAR ADCs)have medium resolution and medium speed,and can be easily realized in CMOS process.Due to the mixed advantages in cost,resolution,speed and power,SAR ADCs have been widely used in bio-medical,wireless sensor network,data storage and soon.Based on the application field of bio-medical,there is a need for a low power consumption,medium speed and resolutio.In this study a 12-bit,60-Ms/s low-power SAR ADC is designed.This design is implemented in a 1.8-V TSMC 0.18-?m CMOS process.This paper studies and designs 4 unit circuits,which are the key components of SAR ADC,to improve the performance of SAR ADC.Firstly,in order to improve the accuracy of sample switch,a new bootstrapped switch is used to realize sample and hold circuit.Secondly,segmented capacitors and monotonic capacitor switch method are used.This design can not only improve the linearity of the DAC,but also reduces the area of DAC and the power consumption of DAC during the process of switch.In order to reduce the mismatch of the capacitor array,a partial common-centric configuration is applied in the capacitor array.Thirdly,in order to reduce the power of comparator,double-tailed dynamic comparators are used.This type of comparator can reduce the delay of comparator.Besides,the power and kickback noise are also reduced.Lastly,in the design of logic control,a new kind of D flip-flop is adopted.This D flip-flop is called True Single Phase Clock(TSPC).This kind of D flip-flop has a simple circuit structure.It costs much lower power and can work at a high speed.This SAR ADC is designed in Cadence' tool.The simulation results of schematic and layout are showed in this paper.The layout occupies the area of 550?m*175?m.The post-simulation results show that:when the sampling speed is 66.67 Ms/s,its signal to noise and distortion is 67.67dB,and spurious free dynamic range is 79.84 dB,thus the effective number of bits is 10.95 bit.The measured power consumption is 9.36 mW.Simulation results show that this design meets the requirements of system.