Design Of Implantable Low-Power High-Speed UWB Transmitter Chip

UWB wireless communication technology provides new technical means for short distancecommunication with the advantages of high-speed, high-security, high-accuracy and lowpower spectrum. The research on UWB Near Field Communication(UWB-NFC) has arisengradually. According to requirements of high speed transmitting in implantable and indoorenvironment combined with UWB receiver, a low compexity, low power and high-speedtransmitter chip without considering multi-path effect should be achieved.Firstly, several kind of existing UWB signal pulses was analyzed, the time domainwaveform and frequency spectrum of these UWB signal pulses are simulated and comparedby the MATLAB software. Secondly, three kind of UWB modulations was analyzed andcompared with each other. Square wave envelope narrow pulse and UWB OOK modulationwere adopted.The chip system adopts a digital on-off VCO UWB pulse generation method and the theoryalgorithm of this method has been tested by MATLAB software. The chip system with thecore cells of narrow pulse generator, digital on-off VCO and tunable gain power amplifiertransmits UWB RF signal in3~5GHz and100Mbps symbol rate. Moreover, the width ofnarrow pulse can be controled and adjusted accurately by changing biasing voltage. Digitalon-off VCO should constantly remain in standby mode so that the oscillation and staticcurrent does not occur, except when the base-band narrow pulse turning up. Since theoscillation occurs only in very short pulse duration (sometimes can be even short to ananosecond), the energy efficiency of the chip is further improved. The stable and reliableoscillation frequency can be realized by the the bias voltage.The total circuit and layout of chip design were achieved in UMC0.18m RF CMOSstandard process with1.8V operating voltage, the total area of chip layout is0.55mm~2. Thepost-simulations indicates that the proposed chip achieved100Mbps symbol rate in3~5GHzwith the UWB signal power spectral density is-45dBm/MHz and total power consumption is13mW. Besides, the width range of narrow pulse generation is1ns~700ps. Moreover, digitalon-off VCO oscilates stably and reliably with the central frequency of4~5.8GHz tunable. It indicates the proposed chip’s functions were implemented successfully.