High Throughput And Customized NoC Implementation Based On FPGA

The development semiconductor manufacturing technology has boosted the integrated degree of digital chip.Recently,numerous Multiple-Processor System on Chip(MPSoC)applications emerge on FPGA.The key to implement the MPSoC is the multicore communication problem.Network on chip(NoC)is an effective infrastructure to make the multicore communication,which motivates the design of FPGA based NoC.This thesis investigates the NoC router architecture in great detail and design high throughput architecture based on the fine-grained configurability and customizability provided by FPGAs.Specifically,we 1)divide the logic operations of the router into two pipelining stages and implement a modified valid/backpressure flow control mechanism to support high frequency and pipelined routing operation;2)explore different buffering schemes to find an architecture which can sustain low queuing delays and propose two buffer allocation optimization algorithm to improve the throughput with the same usage of resource.The experimental results show that the pipelined architecture achieves operation clock frequency to 432 MHz,which is 3.7 times higher than that of an open source FPGA-based NoC,CONNECT,leading to about 3.4 times improvement in the network saturation throughput.After using the optimization algorithm,linear and iterative algorithm can respectively improve 7.7% and 9.3% saturation throughput at most.