Analysis Of The Dv/dt Noise In Smart Power Module

Due to the excellent performance,insulated gate bipolar transistors(IGBTs)are commonly employed as the power switching devices of the Smart Power Module(SPM),where they are required to switching on and off at high frequencies in order to reduce switching dissipation and improve system performance.However,this fast switching transient can lead to problems.One of the main issues caused by this switching transient that should be considered to properly design the SPM is dv/dt problem.In order to improve dv/dt immunity,increase the reliability of both IGBT and SPM itself.It is therefore necessary to explore the theory behind dv/dt induced problem.In this paper,the dv/dt noise in high voltage level shift circuit and three-phase inverter circuit will be focus on.By using parasitic parameters as research variables,we established some dv/dt noise analysis model to find some key factors which can improve the performance and reliability of SPM at the same time.By changing these key factors,The provided design successfully ensure the safety of SPM in high dv/dt noise.The formula and simulation results show that the improved high-voltage level-shif circuit in this paper can reduce the dv/dt noise caused by dv/dt to the 10% of traditional improved high-voltage level-shif circuit.therefore The improved circuit structure can improve the performance while ensuring the security of SPM.The improvement of three-phase inverter circuit is based on the characteristics of IGBT.The spurious gate turn on voltage model is based on the parasitic parameters of IGBT.From this model,we know that the parasitic inductance LS,gate resistance RG,parasitic capacitance CGC are the key factors to influence the spurious gate turn on voltage.Combining latch up effect and the limitation of dv/dt,we described the limitation curve of the dv/dt effect for the three-phase inverter.By Reducing the gate resistance RG,the three-phase inverter circuit can automatically adapt to the speed of dv/dt.