FPGA Implementation Of DOA Estimation Algorithm Based On Sparse Reconstruction

DO A(Direction of Arrival)is the main research content of array signal processing.It has been widely used in the fields of wireless communication,electronic countermeasure,signal source location,medical signal processing and so on.Compressive sensing theory make the data acquisition and the data compression combined,with less data can accurately reconstruct the original signal,which breaks through the limitation of Nyquist sampling theorem.Compared with the traditional DOA estimation algorithm,the DOA estimation method based on the sparse reconstruction algorithm of Compressive sensing theory has good performance in natural decorrelation,high noise immunity and single snapshot measurement,which has been gained extensive attention and been in-depth studied by the scholars.In some areas of real-time requirements strictly,it is very important to study the hardware implementation of DOA estimation methods to meet the needs of practical applications.At first,the basic mathematical model of array signal processing and the basic theory of Compressive sensing sparse reconstruction are introduced in this paper.Then,the two theory are combined to discuss how to use the Compressive sensing sparse reconstruction to estimate the direction of arrival.As the Implementation of the algorithm involves the calculation of matrix inversion,so several matrix inverse algorithms based on matrix decomposition and the problem of complex matrix inverse are introduced.Finally,the hardware implementation of the orthogonal matching pursuit(OMP)sparse reconstruction algorithm based on FPGA is designed for the uniform array of eight elements to perform the DOA estimation by using the modified Cholesky decomposition of the matrix inversion algorithm.The hardware structure consists of the clock module,the address generator,the residual value storage,the sensing matrix memory,the inner product operation module,the inner product comparison unit and the data reconstruction and residual calculation module arithmetic unit,and use the clock signal which is generated bu the clock module as the global clock constraints to cascade the various modules according to their functions.This design uses the MATLAB software to simulate the data which is received by the array,uses Verilog hardware description language for programming under Altera's Quartus ? 13.0 development environment,uses the Synplify Pro tool for comprehensive to get the corresponding RTL(Register Transfer Layer)circuit diagram.Finally,the corresponding function simulation is carried out by means of ModelSim-Altera 13.0 simulation tool,and the simulation results verify the correctness of the design.