Research And Implementation Of Matrix Inversion In Massive MIMO

The need for data transmission has been growing rapidly recently and brings out the requirement that the communication system should have more capacity and be more reliable. Thus, researches on key technologies in the system of next generation communication system have been carried out in-depth and wide-ranging. Massive MIMO, as a key technology with high expectation, declares that the base-station equipped with a lot of attennas will greatly improve the capacity of a communication system,but it will inevitably increase the implementation complexity of the matrix inversion in precoding module. This paper focus on the circumstances that base station equipped with a large number of antennas, analyzes the performance of various linear pre-coding algorithms, then researches the matrix inversion algorithm used in linear pre-coding module, and finally implements the low-latency 8 × 8 and 16 × 16 matrix inversion.Firstly, the achievable capacity of Massive MIMO is introduced, then in terms of pre-coding module, this paper shows the analysis of two common linear pre-coding algorithm, ZF and MMSE. Then a simulation using ZF and MMSE algorithm under multi-antenna environment has been done and the results imply that when the number of base station antennas is far more than the number of terminals, the ZF algorithm can guarantee the performance of the communication system.Then this paper brings out an in-depth research for the matrix inversion algorithms used in linear pre-coding, including QR, LU, cholesky and Neumann Series approximate inversion algorithm. Depending on designing requirements, this paper give out the complexity comparison chart of these algorithms, in which the Neumann Series approximate inverse algorithm require least hardware complexity. Then a simulation for this algorithm in massive MIMO is raised and the results indicates that the proposed Neumann Series algorithm can be done in high-dimensional matrix with low latency and low complexity.Finally, this paper designs and implements 8 × 8 and 16 × 16 matrix inversion using Neumann Series algorithm on FPGA. The distribution of matrix elements has been found along with resource consumption in the mainly used IP core helps us to determine the fixed bit width, in order to ensure the accuracy of the hardware design as well as low resource consumption. When dealing with the matrix multiplication module, we remove out some parts of redundancy calculation module and save a comsiderable number of DSP resources which will decrease the pressure of layout. The timing analysis indicate that these two desigins for matrix of different dimension can both reach a maximum clock frequency of 350 MHz or more, and the operation delay is within 2us, normalized mean square error of 8×8 and 16×16 are-40 dB and- 27 dB. The design can surely meet the requirements of high-frequency as well as high-speed communication systems.