Sata Ii Encryption And Decryption Of Physical Layer Interface Chip Design And System Debugging

With the advent of the information era, hard disk increasingly becoming the main media for information storage. It has developed form the traditional PATA (parallel ATA) hard disk to today's SATA (serial ATA) hard disk. Compare with the traditional PATA(which also called IDE), SATA hard disk using a differential serial transmission technology, which has stronger anti-interference ability, higher transmission rate, lower transmission voltage, significantly cut down the number of pin, support hot-plug, and many other advantages. SATAⅡis the second-generation technology standards of SATA interface, it brings the theoretical transmission rate value from the first generation of 1.5Gbps up to 3Gbps, and this technology-based hard disk are currently the mainstream of the hard disk market.With the security of information storage more and more attention, personal, government departments, financial securities and enterprises have to consider how to prevent the hard disk being stolen. Although encryption by software can work conveniently, it limited by its security level is not enough, easy to be deciphered, occupy too much system resources and lead it to work slowly, especially for the treatment of mass data. Using hardware to encrypt the data can solve those problems. So, combining the SATA interface technology and encryption technology to research and design, realizing hardware decryption control circuit based on SATA interface have very important application and research value.In this dissertation, we analyzed the SATA protocol, including the physical layer, link layer, transport layer, command and application layer. Described the architecture design, module partition, theory of system work of SATAⅡinterface encryption and decryption chip. We focus on how to use Xilinx Virtex-5 FPGA high-speed serial IO-gigabit transceiver (GTP) to carry out the physical layer of this system, and the design has been verified on the board level. How to utilize the limited condition to debug the system effectively, which with high signal width, complexity of functional and interactive, is another important mission of this dissertation. During the process of debugging, we adopted an effective method of debugging, which use the on-line logic analyzer to capture data before and after the fault time, and then export the data, set up testbench, using actual data for fault simulation and recurrence. Finally, we tested the FPGA-based SATAⅡinterface encryption and decryption chip's control circuit, the design has achieved the desired results, which laid a good foundation for the further work of system integration and combine debugging.