VLIS Design Of Intra Prediction And Transform Module In HEVC

High Efficiency Video Coding(HEVC/H.265) is the latest video coding standard proposed by ITU-T Video Coding Experts Group and ISO/IEC Moving Picture Experts Group. Compared with H.264/AVC standard, it reduces bitrate by 50%, but brings more complexity in coding and decoding. This dissertation studies intra prediction and transform prediction to improve the efficiency, and the implemention techniques to reduce the processing delay and area.The main contribution is as follows:1. Hardware architecture design for HEVC intra prediction moduleThe state-of-the-art works in intra prediction still suffer from problems such as large circuit area and low operation frequency, so this thesis focues on the design and optimization of the intra-prediction circuits, especially on the three modes: DC, Planar and Agular. First, the intra prediction algorithm on DC prediction is modified into a two-stage mode, reusing the adders to save area. Second, the hardware architecture for Planar prediction model is optimized by using module reuse and state transfer. Finally,the hardware architecture design for Agular prediction model is optimized by reusing look-up table and special multiplier.The result shows that compared with other works,the DC prediction module increases operation frequency by 40%, saving 32.4% logic gate count and 50% processing cycle; the Planar prediction module increases operation frequency by 62%, saving 51% area and increasing 25% processing cycle; the Angular prediction module improves HE performance by 176%.2. Hardware architecture design for HEVC transform moduleTo reduce circuit area and operation frequency of DST algorithm in transform module, a new DST algorithm is proposed based on the characteristics of the DST matrix coefficients, and a special signal multiplier is designed. Further more a specialized memory for matrix transpose is designed, and a pipelined circuit is aslo desgined to increase operation frequency. Experimental results show that the proposed architecture can save 25.07% area and 33.36% power.