Implementation And Verification Of The High Speed I/O System In SoC System

With the development of modern science and technology and electronic products change rapidly, faster speed, higher bandwidth has become one of the goals for the industry. Under this background, PCIe3.0 protocol emerges as the times require, PCIe3.0 protocol designed by product is becoming more and more common in work and life. At present, PCIe3.0 has become one of the important factors to improve the processor performance.This paper first introduces the development and application of the PCIe bus, then analyzes the content of the PCIe bus protocol, and summarizes the unique characteristics of PCIe3.0. Through the PCIe3.0 IP core reuse technology and AMBA3.0 bus architecture, implementation of high speed I/O system on a SoC chip. The system implements the RC and EP devices of the PCIe3.0 protocol, as well as between the two devices connection. Through the Host bridge of RC equipment to access different devices, launched a DMA request and interrupt request through the EP equipment.This paper built a directional test platform of Verilog language, the configuration of the RC equipment and EP equipment, complete link training and initialization process, so that the two equipment can transmit TLP transaction, then verify the function of the design, and make use of SV language to build t a UVM platform, to establishment random test stimulus. In the test platform, the OVL assertion checker to check the design, such as different types of PCIe3.0 TLP protocol transactions and the key signal of the link.