The Processing Technology Research Of Airborne High Resolution SAR Imaging Agorithm Based On FPGA

Synthetic aperture radar(SAR) is a high resolution imaging radar, which has the ability to penetrate shelter and acquire high resolution target images is widely used for battlefield surveillance, environmental monitoring, emergency relief, for its advantages of all time, all weather and strong over traditional optical imaging and infrared remote sensing. SAR is different from traditional radars which just detect target location for it can capture the image of targets, get more target information and realize better object identification. SAR is mainly carried by satellite and aircraft and difficulty applied to mini flying platform for complex system, high cost, large weight, large in size and so on. With the development of mini aircraft and small unmanned aerial vehicle both at home and board, using mini flying platform to carray SAR has been paid close extensive attention. However, these problems such as size, weight, power comsumption and real processing are urgently need to be sloved at first. In order to built miniature SAR, processing algorithms should be simple processing and suitable for hardware implementation. Polar format algorithm(PFA) can bring to the principle of chirp scaling(PCS) to replace the interpolation by complex operation and fast Fourier transforms(FFT) in broadside mode, which extremely reduces the computational complexity. On the other hand, the rapid development of programmable devices mades filed programmable gate array(FPGA) widely applied on the occasion of high rate and large amount of data processing for the features of hardware programmable and parallel processing. Therefore,using FPGA to implement algorithms of SAR is becoming a hot research area without doubt. This paper is divided into five chapters, and the main content of each part is as follows:Chapter 1 is the introduction of the thesis. The history of SAR and the development of miniature of SAR at home and board are reviewed, and the development of FPGA based parallel processing technology is outlined. The significance of the implemention of FPGA to achieve rapid PFA on mini SAR system is discussed. The structure and main content of the paper is illustrated at the end of this chapter.Chapter 2 introduces the PFA. Firstly, the dechirped signal is introduced. Secondly, using interpolation method and PCS method to implement PFA is described separately. What's more, according to the realization approaches of PFA, point target echo simulation results presented. Further more, the advantages of PGA based on PCS in terms of hardware implementation analysed.Chapter 3 discusses the implementation of FPGA on-chip high-speed processing. Considering the process flow of PFA and FPGA technique for SAR real-time processing, system designs three functional sub-modules which includes the algorithm sub-module, the DDR3 sub-module and the PCIe transport sub-module in order to save the hardware resource and improve the efficiency of real time data processing. Then the function, efficiency and deviation of each sub-module are analysed.Chapter 4 mainly discussed system validation and data analysis. System makes use of VC707 evaluation board as hardware development platform and combines with other hardware and software resources(PC machine, DDR3 SDRAM, etc). Taking three functional sub-modules into consideration, system realizes the algorithm control process. In order to verify the system feasibility, the size of 8192*8192 dechirped signal imports to SAR signal processing system and compares the FPGA process result with MATLAB process result at last.The research achievements are summarized, and follow-up research direction is proposed.