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Fast Polar Format Algorithm And Its FPGA Implementation

Posted on:2014-09-09Degree:MasterType:Thesis
Country:ChinaCandidate:L C ZouFull Text:PDF
GTID:2298330422480613Subject:Signal and Information Processing
Abstract/Summary:PDF Full Text Request
Synthetic aperture radar (SAR) is an important technology in modern remote sensing field. Polarformat algorithm (PFA), with its high efficiency and simple procedure, is widely used in spotlightSAR imaging. However, the computational efficiency and the precision of the traditional PFA islimited by the interpolation process involoved. The using the principle of chirp scaling (PCS) canreplace the interpolation with fast Fourier transforms (FFT), which reduces the computationalcomplexity. On the other hand, the rapid development of programmable devices makes fieldprogrammable gate array (FPGA) widely applied, and has become the inevitable trend ofdevelopment in radar imaging. This paper mainly researches on the FPGA implementation of fastPFA.Firstly, the traditional PFA is discribed. Then, from the viewpoint of signal coupling, theinterpolation processing for range migration correction is analysed, and the essence of conversionfrom polar coordinates to Cartesian format is revealed. In order to use the essence of scaling, the PCSand the corresponding transformation is discussed in detail. The simulation of the point targetresponse is applied to verify the feasibility of the algorithm. Secondly, to realize on-chip high-speedprocessing, three functional sub-modules are proposed according to the fast PFA: the algorithmsub-module is designed to realize the two-dimensional compression processing; the DDR3sub-module is designed to achieve high-speed transposition of two-dimensional matrix; the Ethernetcommunication sub-module is designed to accomplish the data transmission between the PFGA andhost. Then the function, efficiency and deviation of each sub-module are analysed. Then the overalldesign of the FPGA implementation of fast PFA is proposed, including the control sub-module and aspecial parallel structure. Finally, to verify the feasibility of the design, the validation system isaddressed according to the architecture of the KC705development board. The result of point targetresponse and read-data processing is illustrated and the performance is analysed. The researchachievements are summarized, and follow-up research direction is proposed.
Keywords/Search Tags:SAR, polar format algorithm, princeple of chirp scaling, FPGA, DDR3
PDF Full Text Request
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