| According ITRS Roadmap and Moore’s Law, the technology node, namely critical gate length, will be shrunk by 30 % for every 2 years. Generally, different generation of technology node has different design rule, device requirement and SPICE model, and supply voltage. To go for direct shrink is a Hercules task because it involves time-consuming, big financial spending, and huge human resource support. Thus, to reduce cost spending and development time, fab-less IC design houses prefer direct shrink but maintaining the same supplied voltage, while minimizing the change of device requirement, SPICE model, and design rule. Direct shrink is business demand with core value of cost reduction, and such half-node technology is generally offered by foundries. However, the direct shrink methodology, process integration, reliability and yield improvement topic of half-node technology was seldom reported. This thesis addressed in above topic, to provide valuable knowledge in solving practical problem of IC foundries.Firstly the superiority of mask level direct shrink is demonstrate and shrink methodology is introduced. Base on IC design margin and process margin analyse, a SRAM bitcell shrink is evaluated in both design scope and process scope. Satic noise margin is simulated by HSPICE with different models and sizes of both orginal and new techlogy. Compareing the result, we see it’s shrinkable from design point of view. Since the bitcell in customer GDS file is post-OPC layout, 2 shrink strategies are process-simulated. One strategy is base on post 0.15um OPC data direct shrink without 0.14um OPC, the other strategy is restore the orginal(or pre-OPC) layout, then do direct shrink followed by 0.14um OPC operation. We get data proven that the latter one has better process margin.Secondly process evaluation, adjustment, optimization of shrink technology is studied by CMOS process sequence. For 0.15um shrink to 0.14um technology, we demonstrate the existing STI loop process is capable in new technology, through various aspect of process margin check. Gate shrink feasibility is reviewed. Considering minimal pitch change and existing process margin, photo process depth of focus is below 0.3um. So advanced photo resist was adopted and new OPC was developed to enlarge photo depth of focus.For backend interconnect,wire length and width both shrink to 93% according layout shrinkage.Both wire resistance and intra-layer capacitance will keep the same if metal stack and thickness unchanged. To keep inter-layer capacitance, we shoud reduce inter-metal- dielectric by a facor of 0.93*0.93,due to metal area is reduced by a same factor from layout shrink. After shrink, the IMD gap fill becomes a concern because aspect ratio increased. We optimized HDP-Oxide deposition/sputter ratio to achieved void-free gap fill. The theis also addressed device characteristic related implant optimization; we observed Vt-roll-Off curve flattened when reducing LDD and pocket implant at same time.Finally comes to reliability and product yield of half-node technology, we foucs on 2 topics here, aluminium wire electronic migration and systematic Cp yield problem. EM is quite a challenge because wire width reduced but stress current unchanged. We demostrate that EM could be improved by separating Ti/TIN and Al sputter into different process steps. With stastic analyse and correlation study, we recognize STI process is a systematic factor of yield loss. We reduced STI CMP post thickness and implement dynamic control HF remove amout during SIN remove process, thus solved yield loss problem and achieved comparable yield of 0.15LV technology. |
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