The Research And Implementation Of Encoding And Decoding Technology Based On Satellite TT&C

Satellite telemetry and telecontrol & communication(TT&C) system is an important tache of satellite communication link, which guarantee the normal operation of the satellite communication system. Whereas, due to unideal transmit characteristic of satellite channel,the information could be distorted when the TT&C transponder communicate with ground station. So, how to improve the communication reliability of the TT&C system become a hot and difficult problem in the field of satellite TT&C. In addition to the anti-interference technology and spectrum technology, error correction coding is the key technology to enhance the reliability of communication of TT&C system.The satellite channel is Gauss white noise channel, generally appears random errors,sometimes appears burst errors, so we should take measures to deal with both the random errors and burst errors. Not only does the appropriate error correction coding technology can effectively reduce the bit error rate(BER), but also improve the anti-jamming performance, so the error correction coding is an indispensable part of satellite TT&C system. The main study and achievements of the thesis are as follows:Firstly, This paper introduces the relevant algebra theory of error correction coding technology and the knowledge of linear block codes, includes the concept, cyclic codes,and truncated code. In addition, this paper discusses the principle of several commonly used error correction codes. Secondly, based on the characteristics of data transmission, and combined with channel type, BER performance, coding efficiency and coding complexity,the article carries out a detailed design of error correcting coding: up-link decoding adopts truncated BCH(104,48) and down-link coding employs RS(242,210) truncated codes strategy which correspond to the CCSDS standard.Finally, the paper designs the hardware scheme on the basis of theoretical analysis, and describes the specific function, port definition and process logic diagram of every module.Furthermore, the design is implemented on FPGA virtex-5 200 T by using VHDL, and the thesis gives the simulation results of Model Sim and resource usage. In addition, the RS encoder ? BCH encoder and decoder designed in this paper have completed the project implementation, and applied to a major project, also have gained excellent performance.