The Design And Implementation Of FFT In OFDM Systems Based On FPGA

With the evolution of communication standards, LTE/LTE-A (Long Term Evolution/Long. Term Evolution-Advanced) has been adopted as the new generation standard of wireless baseband communication. The OFDM (Orthogonal Frequency Division Multiplexing) is the kernel technology of LTE/LTE-A systems, which has high utilization of frequency spectrum that makes it the premier choose for high-speed information transmitting. Furthermore, FFT/IFFT is the kernel operation of the data processing in OFDM systems and the key to the quadrature modulation and demodulation. The results of FFT/IFFT influence the performance of OFDM directly, thus the study of it is very important to the realization and optimization of LTE/LTE-A systems.In this thesis, the analysis and the hardware implementation of FFT are discussed, in order to achieve a scalable, high throughput and easy-control architecture with simple mechanism. The pipelined FFT accelerator is designed after the analysis of the algorithm and its memory accessing characteristics. The algorithms adopted in this thesis are the radix-2 and radix-22-DIF FFT, and the architecture is the structure of MDC with input operation of Ping-Pong mode to accomplish the seamless buffering and managing. Based on the fact that the twiddle factors in this structure are too huge and the mismatching between sequential reading the twiddle rotation factor with computing.In this thesis, the storage of twiddle factors is optimized and the total computation performance is improved. According to the analysis of the storage characteristics, various step data accessing mechanism is proposed to ensure the right twiddle factor is accessed.In addition, the seamless pipeline in this thesis requires the data adjusted to be right after each stage to match the butterfly computation in next stages. To solve this, the data merge model facing to the next stage of computing is designed to guarantee the right time sequent. At last, the data is output through the bit inverse order output module.The proposed architecture has been synthesized for the Spartan-3E XC3S1200E-4FG320 FPGA. The software environments are Modelsim, ISE, Synplify Pro and Matlab. Experimental results show that the proposed MDC-FFT architecture works on the maximum clock frequency of 150MHz and can realize the FFT of 128/256/512/1024/2048/4096 points. With the suitable hardware resources, the longest symbol processing time is 40.635?s, which satisfy the LTE-A standard and performs 5%?46.8% than other architectures. The advantage of variable length is also impressing.