Research And Design Of OFDM Demodulate Circuit For DAB And CDR

The digitization of analog broadcasting is an inevitable trend.At present,there are two industry standards in China: Digital Audio Broadcasting(DAB)and China Digital Radio(CDR).The two have their own advantages and disadvantages and may coexist for a long time.The development of a demodulation chip that can support two systems at the same time is very important for the development of digital broadcast receiving terminals.The core circuits of the DAB and CDR demodulation chips both use Orthogonal Frequency Division Multiplexing(Orthogonal Frequency Division Multiplex,OFDM)technology,but there are significant differences in the specific configurations such as the number of carriers,carrier spacing,and symbol duration.In this paper,according to the characteristics of OFDM modulation in DAB and CDR standards,a multi-mode parameter-configurable multi-mode configurable Fast Fourier Transform(FFT)processor is designed.With this as the core,OFDM compatible with DAB and CDR is designed.Demodulate the circuit and verify it in the Field-Programmable Gata Array(FPGA).The main content of the thesis is as follows:1.Analyze the principle of OFDM demodulation and study various algorithms and hardware implementation methods of FFT circuit of OFDM demodulation key operation module.Considering the chip area and cost,as well as the DAB and CDR requirements for demodulation time,the optimized base-2 / 4 mixed base algorithm are selected.2.In response to the operation requirements of the multi-mode variable-point FFT circuit,which is the core function of the OFDM system,the mixed basis algorithm uses pipeline R2 SDF and R22 SDF structures,and configures a different number of butterfly units through the controller to realize variable-point FFT operation,and at the same time through the multiplex adder And multiplier to save hardware resources.3.Using Modelsim for timing simulation,the results show that in DAB mode,the circuit only needs a maximum operating frequency of 4 MHz to meet the needs of demodulation operations,and the OFDM demodulation time of 256/512/1024/2048 points is about 0.12/0.25/0.51/1.02 ms;In CDR mode,the circuit only needs a maximum operating frequency of 0.2 MHz to meet the needs of demodulation operations.The 128/256 points OFDM demodulation time respectively is 1.27/2.55 ms.Based on Xilinx Artix-7 XC7A35 T synthesis,the results show that: this design consumes 2394 registers,12 RAM,5800 lookup tables,20 multipliers.Adopt TSMC CMOS 130 nm technology for synthesis and the results show that the effective area of the circuit is 0.475 mm2.Under the 4 MHz system clock,the power consumption is about 0.77 m W.At the 0.4 MHz operating frequency,the power consumption is about 0.04 m W.It has the advantages of low power consumption and many operation modes.