Research Of TSV Defect Detection Method For 3-D Integrated Circuits Before Binding

With the rapid development of integrated circuits technology, the three dimensional integrated circuits (3-D ICs) based on the Through Silicon Vias (TSVs) technology, because of low latency, high integration and low power consumption, are widely used in the industry. The interconnection delay of IC dies can be significantly reduced by binding with the TSV structure and corresponding chip performance can be improved. However, during the manufacturing and binding process, the TSVs can be easily produced with unpredictable defects such as leakage defects. The dies stacked with defective TSV ultimately result in the failure of 3-D ICs products and grievous decrease of the yield. Therefore, detection of the TSV defect is dramatically desired before die binding to prevent the blending of defective TSV on the stacked integrated of 3-D ICs. It is also concerned to improvement of the yield of 3-D ICs and reduction of the manufacturing cost of the object.In this paper, a TSV leakage defects detection structure is proposed to effectively detect the TSV leakage defects before the binding. This approach is based on the capacitance and resistance characteristic of TSV and TSV leakage current is converted to a voltage value which can be tested with proposed structure. Specifically, a programmable test signal generator is applied to charge the TSV to in a high impedance state at the expected time. After a certain time interval, the floated voltage of TSV is sampled and based on the sampling results to determine whether there is a leakage defect of TSV. The simulation experiment results demonstrate that the proposed leakage detection structure is able to provide a wide scope of TSV leakage defect detection with relatively low manufacturing cost, low power consumption.