The Design Of Image Processing Module Circuit Based On SOPC

With the development of mobilie Internet and information technology, the transmission of multimedia data such as images and videos in the wirelsss channel is becoming more and more important. However, the bandwith of the wireless channel is limited and the people's requirement for the quality and speed of image transmission is becoming higher and higher so that the traditional still image compression standard JPEG fails to meet these requirement. With this background, JPEG2000 is proposed and published by International Standard Organization(IS O) and International Telecommunication Union(ITU) as a new still image compression standard. JPEG2000 supports both lossy and lossless compression and progressive transmission according to the quality or the resolution. It also supports the coding of the region of interest and can maintain good image quality when the bit rate is low. Therefore JPEG2000 enjoys broad prospects in many fields such as mobilie Internet.SOPC is a kind of system on programmable chip for embedded system development.It is based on FPGA and integrates the processor, memory, I/O and various programmable logic, etc.SOPC also has many advantages such as low-cost, flexible design, high processing speed and upgrading. This thesis is based on the technology of SOPC and designs architecture of the JPEG2000 coding system.This thesis makes a research on the JPEG2000 standard and mainly focuses on the part of Tier-1 coding which includes bit plane coding and arithmetic coding.This thesis also make a study on the coding of the region of interest and designs a circuit module which truncates the region of no interest in advance based on the improved algorithm of ROI. The circuit can recognize the code block which is not in the range of ROI and truncate its coding. Therefore, the circuit saves the resource consumption of the system and improves the system coding efficiency on the premise of ensuring the quality of the images. This thesis also researches the file structure and code stream organization of JPEG2000 and designs a circuit which is used to output the codestream.The circuits designed in this thesis are all described by Verilog HDL language and simulated in Modelsim and Matlab. Besides, the circuits are synthesized and implemented by Xilinx's XC7Z020-CLG484-1 FPGA. Experimental results show that the maximum operating speed is 147 MHz and logic cost is 21144 slices.