Physical Design Of Dual-Core Cortex-A9 Processor Chip Based On 28nm Process

With the continuous progress of the process, the feature size is narrowing down, while the size of integrated circuit is getting increased, which brings new challenges to IC design. In ultra deep micron process, because power supply voltage decreases, interconnect delay increasingly becomes a dominant factor in path delay and process deviation and crosstalk phenomenon increase, it brings many challenges and puzzles to the physical design. It is worthy that studying and improving the physical design based on new process to shorten design cycle and design a chip with of better performance, smaller size and lower power consumption.The physical design of a dual-core Cortex-A9 processor chip based on 28nm process is studied in the paper. Firstly, the overall structure of chip is analyzed as well as the performance and components of the main functional modules. Then, many details are studied and discussed in each phase of backend process, which includes floorplan, powerplan, placement, clock tree synthesis, routing and chip verification. In the floorplan phase, die size is determined, and macro cells, special cells and I/O cells are also placed. In the powerplan phase, power domain, power, ground and their connection are defined, then power rings and strips are designed. In the placement phase, as the increasing complexity of interconnect delay leads to the inconsistency of the timing and congestion results between the placement and synthesis stage, we improve the process and adopt advanced dcg placement flow to realize the interaction of layout information to improve timing and congestion. In the critical CTS stage, considering the on-chip variation and clock gating technology which make traditional cts method achieve the goal of minimizing clock skew, the more advanced clock concurrent optimization technology is used to complete synchronously clock tree synthesis and optimization. The useful skew is exploited at the greatest extent. The new cts technology not only effectively reduces the area and power consumption of the clock tree, but also increases the frequency of the chip by 6%. Many methods to prevent and repair antenna effect and crosstalk are implemented during the routing process. Finally, chip verification is also completed.In this paper, the physical design and verification of dual-core A9 processor chip based on SMIC28nmHKMG process are completed. The result shows that the total cell count is 1.57million. The chip's width is 5299?m and the length is 5300?m. Meanwhile, the IR-drop proportion is not less than 5% with the frequency of 1.3GHz and the power consumption of 2.3W, which meet the requirement Therefore, the proposed processor chip has a promising application in high-performance processor.