Design And Simulation Of Multi-Mode Digital Communication System Transmitter

Multi-mode wireless transceiver is a hot topic research both at home and abroad, its main characteristic is on the general hardware platform to realize different ways and a variety of parameters of information transmission by using the controller. Among them, the emergence of the software radio technology and the smart antenna accelerated the development of multi-mode digital transmitter. Research based on the FPGA(Field-Programmable Gate Array)of multi-mode digital transmitter has received extensive attention by its unique advantage, including digital frequency synthesizer DDS(Direct Digital Synthesizer) based on FPGA, intermediate frequency modulation and demodulation based on software radio, all-purpose encoder and decoder, all-purpose synchronizer and all-purpose filter, etc.According to the requirements of the electronics and communications professional practice teaching, this paper design a full digital multi-mode transmitter, the design uses the FPGA technology, and adopts the modular, hierarchical design method, meet the relevant experiments and practice teaching (including single module and multi-module of validation, design and integrated experiment). The cntent mainly includes all-purpose modulator, channel encoder, interleaver, time division multiplexer and digital up mixer, etc. In addition to the various modules, the focus of the research mainly is the allocation of system resources and the interface between the various modules in order to achieve the requirements of all kinds of practice teaching.Refer to relevant data, on the basis of previous studies this paper design the structure of multi-mode transmitter, and the part of the design is optimized. Specific content including intermediate frequency modulator based on DDS, all-purpose channel encoder and all-purpose time-division multiplexer, etc. Implementation of the modulator can achieve basic modulation and orthogonal modulation, a total of five kinds of digital modulation; Three channel coding method including interleaving are implemented, and the interleaver can achieve a variety of interleaving depth and length; The design of time division multiplexer can realize arbitrary signal time division multiplexing. In addition to the above, the related design task also includes completing the DDS carrier generator for up mixer, test signal source and the interface between FPGA and controller.This paper completes the corresponding hardware circuit and program design, at the same time, each module are simulated and analyzed. And under the parameters of single user baseband code rate of 64 Kbps,2-6 paths signal time division multiplexing, coding rate up to 3.584 Mbps and the highest frequency of modulation carrier is 17.92 MHz for simulation and analysis to the system.The results show that the design scheme is correct and feasible, and the function and indexes can meet the design requirements.